Semiconductor devices and methods of manufacturing the same

Patent metadata

Field	Value
Publication number	US-9349633-B2
Application number	US-201414563269-A
Country	US
Kind code	B2
Filing date	Dec 8, 2014
Priority date	Dec 6, 2013
Publication date	May 24, 2016
Grant date	May 24, 2016

Abstract

A method of manufacturing a semiconductor device includes forming an isolation layer on a substrate, where an active pattern is defined, forming an insulating interlayer on the active pattern of the substrate and the isolation layer, removing portions of the insulating interlayer, the active pattern and the isolation layer to form a first recess, forming a first contact in the first recess on a first region of the active pattern exposed by the first recess, removing portions of the active pattern and the isolation layer in the first recess by performing an isotropic etching process, to form an enlarged first recess, and
filling the enlarged first recess to form a first spacer that surrounds a sidewall of the first contact.

First claim

What is claimed is:

1. A method of manufacturing a semiconductor device, comprising:
forming an isolation layer on a substrate, wherein an active pattern is defined, the active pattern including a material substantially the same as that of the substrate;
forming an insulating interlayer on the active pattern of the substrate and the isolation layer;
removing portions of the insulating interlayer, the active pattern and the isolation layer to form a first recess;
forming a first contact in the first recess on a first region of the active pattern exposed by the first recess;
removing portions of the active pattern and the isolation layer exposed by the first recess by performing an isotropic etching process, to form an enlarged first recess; and
filling the enlarged first recess to form a first spacer that surrounds a sidewall of the first contact.

2. The method as claimed in claim 1 , further comprising:
forming a bit line on the first contact and the insulating interlayer, wherein the bit line extends parallel to a top surface of the substrate in a first direction; and
forming a plurality of second spacers that surround a sidewall of the bit line.

3. The method as claimed in claim 2 , wherein forming the enlarged first recess is performed after forming the first contact and forming the bit line.

4. The method as claimed in claim 2 , wherein forming the enlarged first recess is performed before forming the first contact and forming the bit line.

5. The method as claimed in claim 2 , wherein the first spacer has a first width in a second direction perpendicular to the first direction, the second spacer has a second width in the second direction, wherein the first width is greater than or equal to the second width.

6. The method as claimed in claim 2 , wherein filling the enlarged first recess to form the first spacer includes:
forming a first insulation layer on an inner wall of the enlarged first recess, a sidewall of the first contact, and a top surface of the insulating interlayer;
forming a second insulation layer on the first insulation layer; and
removing upper portions of the first insulation layer and the second insulation layer.

7. The method as claimed in claim 6 , wherein the first insulation layer includes silicon oxide, and the second insulation layer includes silicon nitride.

8. The method as claimed in claim 7 , further comprising:
removing portions of the insulating interlayer, the active pattern and the isolation layer by an anisotropic etching process to form a second recess between the second spacers, wherein the second recess exposes a second region of the active pattern, and
removing portions of the insulating interlayer, the active pattern and the isolation layer by an isotropic etching process to enlarge the second recess.

9. The method as claimed in claim 8 , wherein an etching solution used by the isotropic etching process has an etch rate with respect to the silicon nitride that is less than the etch rate with respect to the silicon oxide.

10. The method as claimed in claim 8 , further comprising:
filling the enlarged second recess with a second contact; and
forming a capacitor electrically connected to the second contact.

11. A method of manufacturing a semiconductor device, comprising:
removing portions of an insulating interlayer, an active pattern and an isolation layer on a substrate to form a first recess, the active pattern including a material substantially the same as that of the substrate;
forming a first contact in the first recess on a first region of the active pattern exposed by the first recess;
forming a bit line on the first contact and the insulating interlayer, wherein the bit line extends parallel to a top surface of the substrate in a first direction;
removing portions of the active pattern and the isolation layer in the first recess by performing an isotropic etching process, to form an enlarged first recess;
filling the enlarged first recess to form a first spacer that surrounds a sidewall of the first contact; and
forming a plurality of second spacers that surround a sidewall of the bit line.

12. The method as claimed in claim 11 , further comprising forming the isolation layer is on a substrate, wherein the active pattern is defined; and forming the insulating interlayer on the active pattern of the substrate and the isolation layer.

13. The method as claimed in claim 11 ,
wherein filling the enlarged first recess to form the first spacer includes:
forming a first insulation layer on an inner wall of the enlarged first recess, a sidewall of the first contact, and a top surface of the insulating interlayer;
forming a second insulation layer on the first insulation layer; and
removing upper portions of the first insulation layer and the second insulation layer, and further comprising:
removing portions of the insulating interlayer, the active pattern and the isolation layer by an anisotropic etching process to form a second recess; and
removing portions of the insulating interlayer, the active pattern and the isolation layer by an isotropic etching process to enlarge the second recess,
wherein an etching solution used by the isotropic etching process has an etch rate with respect to the second insulation layer that is less than the etch rate with respect to the first insulation layer.

14. The method as claimed in claim 11 , wherein forming the enlarged first recess is performed after forming the first contact and forming the bit line.

15. The method as claimed in claim 11 , wherein forming the enlarged first recess is performed before forming the first contact and forming the bit line.

16. The method as claimed in claim 11 , wherein the first spacer has a first width in a second direction perpendicular to the first direction, the second spacer has a second width in the second direction, wherein the first width is greater than or equal to the second width.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Dae-Ik
• Kim Sung-Eui
• Kim Hyoung-Sub
• Choi Sung-Kwan

Classifications

• H10W20/01 Primary

  Manufacture or treatment · CPC title

• H10D1/716

  having vertical extensions · CPC title

• H10D1/042 Primary

  using deposition processes to form electrode extensions · CPC title

• H10B12/34

  the transistor being at least partially in a trench in the substrate · CPC title

• H10B12/315

  with the capacitor higher than a bit line · CPC title