WLCSP with transparent substrate and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-11742437-B2
Application number	US-202117187510-A
Country	US
Kind code	B2
Filing date	Feb 26, 2021
Priority date	Mar 27, 2020
Publication date	Aug 29, 2023
Grant date	Aug 29, 2023

Abstract

The present disclosure is directed to a package, such as a wafer level chip scale package (WLCSP), with a die coupled to a central portion of a transparent substrate. The transparent substrate includes a central portion having and a peripheral portion surrounding the central portion. The package includes a conductive layer coupled to a contact of the die within the package that extends from the transparent substrate to an active surface of the package. The active surface is utilized to mount the package within an electronic device or to a printed circuit board (PCB) accordingly. The package includes a first insulating layer separating the die from the conductive layer, and a second insulating layer on the conductive layer.

First claim

The invention claimed is:

1. A device, comprising:
a transparent substrate including a first surface, a second surface opposite to the first surface in a direction directed from the first surface towards the second surface, and sidewalls transverse to the first surface and the second surface;
a molding compound on the sidewalls of the transparent substrate;
a die on the second surface of the transparent substrate, the die including:
a sensor aligned with the transparent substrate;
a contact that extends outward from an edge of the die and away from the sensor in a transverse direction transverse to the direction; and
an electrical connection having a first end coupled to the sensor and a second end coupled to the contact;

a first insulating layer on the die and on the contact of the die; and
a conductive layer on the first insulating layer, the conductive layer including:
a first end portion on the first insulating layer; and
a transverse portion on the first insulating layer, the transverse portion is transverse to the first end portion, is transverse to the contact, and is coupled to the contact.

2. The device of claim 1 , further comprising:
a second insulating layer on the first insulating layer, the conductive layer, and the molding compound; and
an opening in the second insulating layer, the opening exposing a portion of the conductive layer, and
wherein the conductive layer further includes a second end portion transverse to the transverse portion and is closer to the second surface of the transparent substrate portion than the contact of the die.

3. The device of claim 2 , wherein the molding compound has a surface substantially flush with a surface of the second insulating layer.

4. The device of claim 1 , further comprising:
a cavity between the die and the transparent substrate, the cavity being adjacent to the sensor of the die; and
a nonconductive layer on the transparent substrate and between the contact of the die and the transparent substrate.

5. The device of claim 4 , wherein a surface of an end of the nonconductive layer is substantially flush with a surface of the molding compound.

6. The device of claim 1 , wherein the molding compound is an opaque material.

7. The device of claim 1 , wherein:
the transparent substrate has a central portion having a first height extending in the direction;
the sidewalls have a second height less than the first height of the central portion of the transparent substrate, the second height extending in the direction; and
the die is on the central portion of the transparent substrate.

8. A device, comprising:
a transparent substrate including:
a center;
a first surface;
a second surface opposite the first surface;
a central portion at the center, the central portion having a first height extending from the first surface to the second surface in a direction directed from the first surface to the second surface; and
a peripheral region surrounding the central portion, the peripheral portion including sidewalls transverse to the first surface and the second surface, the sidewalls having a second height extending in the direction directed from the first surface to the second surface of the transparent substrate, the second height being less than the first height;

a molding compound on the sidewalls of the transparent substrate, the molding compound having the second height; and
a semiconductor die on the transparent substrate, the semiconductor die including a conductive contact on the transparent substrate that extends outward from an edge of the semiconductor die.

9. The device of claim 8 , wherein the transparent substrate further
comprises a connecting portion that surrounds the central portion, the connecting portion connects the central portion to the peripheral portion and has a third height in the direction, and the third height varies between the first height and the second height.

10. The device of claim 9 , wherein the first surface of the transparent substrate further comprises a surface of the central portion, a surface of the peripheral portion surrounding the surface of the central portion, and a surface of the connecting portion connecting the surface of the peripheral portion to the surface of the central portion.

11. The device of claim 10 , wherein the surface of the connecting portion of the first surface of the transparent substrate portion is an inclined surface.

12. A method, comprising:
coupling a semiconductor wafer to a first surface of a transparent wafer;
singulating the semiconductor wafer and the transparent wafer forming a plurality of substrate assemblies, each substrate assembly including a transparent substrate and a semiconductor die coupled to each other;
coupling the plurality of substrate assemblies to a carrier support;
forming a molding compound on the plurality of substrate assemblies and the carrier support;
decoupling the carrier support from the plurality of substrate assemblies and the molding compound;
forming a plurality of trenches in the plurality of substrate assemblies and in the molding compound;
forming a first insulating layer on the plurality of substrate assemblies and the molding compound;
extending the plurality of trenches further into the plurality of substrate assemblies, into the molding compound, and into the first insulating layer;
forming a conductive layer with an end closer to a second surface of the transparent wafer opposite to the first surface of the transparent wafer than contacts of the substrate assemblies, on the first insulating layer, on contacts of each of the substrate assemblies, and into the first insulating layer; and
forming a plurality of packages by singulating the plurality of substrate assemblies and the molding compound.

13. The method of claim 12 , further
comprising forming a second insulating layer in the trenches and on the conductive layer.

14. The method of claim 13 , wherein extending the plurality of trenches further comprises removing portions of electrical contacts of each of the semiconductor die of the plurality of substrate assemblies.

15. The method of claim 12 , wherein the semiconductor wafer and the transparent wafer are 12-inch wafers, and the carrier support is an 8-inch glass carrier substrate.

16. The method of claim 15 , further comprises forming an 8-inch wafer by forming the molding compound and decoupling the carrier support from the molding compound and the plurality of substrate assemblies.

17. The method of claim 12 , wherein forming the plurality of packages by singulating the plurality of substrate assemblies and the molding compound further comprises forming a layer of the molding compound on sidewalls of each of the transparent substrates of the plurality of substrate assemblies.

18. The method of claim 12 , extending the plurality of trenches further into the plurality of substrate assemblies and the molding compound further comprises forming a raised portion of each of the transparent substrates of the plurality of substrate assemblies.

19. The method of claim 12 , further comprising planarizing the molding compound and the plurality of substrate assemblies forming a surface of the molding compound flush with surfaces of each of the semiconductor dies of the plurality of substrate assemblies.

20. The method of claim 12 , wherein:
coupling the plurality of substrate assemblies to the carrier support further comprises spacing each of the substrate assemblies apart from each other; and
forming

Assignees

• St Microelectronics Ltd
• St Microelectronics Pte Ltd

Inventors

• Gani David
• Kuo Yiying

Classifications

• H10P54/00

  Cutting or separating of wafers, substrates or parts of devices · CPC title

• H10F77/933

  for devices having potential barriers · CPC title

• H10F77/169

  Thin semiconductor films on metallic or insulating substrates · CPC title

• H10F77/93

  Interconnections · CPC title

• H10F71/1395

  for thin-film devices · CPC title