Electric storage device
US-9123918-B2 · Sep 1, 2015 · US
US9282261B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9282261-B2 |
| Application number | US-201414557271-A |
| Country | US |
| Kind code | B2 |
| Filing date | Dec 1, 2014 |
| Priority date | May 30, 2012 |
| Publication date | Mar 8, 2016 |
| Grant date | Mar 8, 2016 |
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A method for producing an image pickup apparatus includes: a process of cutting an image pickup chip substrate where electrode pads are formed around each of the light receiving sections to fabricate image pickup chips; a process of bonding image pickup chips determined as non-defective products to a glass wafer to fabricate a joined wafer; a process of filling a sealing member among the image pickup chips on the joined wafer; a machining process including a thinning a thickness of the joined wafer to flatten a machining surface and a forming through-hole interconnections, each of which is connected to each of the electrode pads; a process of forming a plurality of external connection electrodes, each of which is connected to each of the electrode pads via each of the through-hole interconnections; and a process of cutting the joined wafer.
Opening claim text (preview).
What is claimed is: 1. A method for producing an image pickup apparatus, the method comprising: a process of cutting an image pickup chip substrate where a plurality of light receiving sections are formed on a first main face and electrode pads are formed around each of the light receiving sections to fabricate a plurality of image pickup chips; a process of bonding the first main face of each of the image pickup chips determined as non-defective products to a transparent support substrate different from the image pickup chip substrate in at least either size or shape via a transparent adhesive layer to fabricate a joined wafer; a process of filling a sealing member among the plurality of image pickup chips bonded to the joined wafer; a machining process comprising a process of machining the joined wafer to thin a thickness of the joined wafer, from a second main face side to flatten a machining surface and a process of forming through-hole interconnections, each of which is connected to each of the electrode pads; a process of forming a plurality of external connection electrodes, each of which is connected to each of the electrode pads via each of the through-hole interconnections, on the second main face; and a process of cutting and individualizing the joined wafer. 2. A method for producing a semiconductor apparatus, the method comprising: a process of cutting a semiconductor chip substrate where a plurality of semiconductor circuit sections are formed on a first main face and electrode pads are formed around each of the semiconductor circuit sections to fabricate a plurality of semiconductor chips; a process of bonding the first main face of each of the semiconductor chips to a support substrate via an adhesive layer to fabricate a joined wafer; a process of filling a sealing member among the plurality of semiconductor chips bonded to the joined wafer; a process of machining the joined wafer from a second main face side; and a process of cutting the joined wafer. 3. The method for producing a semiconductor apparatus according to claim 2 , wherein semiconductor chips determined as non-defective products in an inspection are bonded to the support substrate. 4. The method for producing a semiconductor apparatus according to claim 3 , wherein the machining process comprises a process of machining the joined wafer to thin a thickness of the joined wafer to flatten a machining surface and a process of forming a plurality of external connection electrodes, each of which is connected to each of the electrode pads, on the second main surface. 5. The method for producing a semiconductor apparatus according to claim 4 , wherein the machining process comprises a process of forming through-hole interconnections, each of which connects each of the electrode pads and each of the external connection electrodes before the process of forming the external connection electrodes. 6. The method for producing a semiconductor apparatus according to claim 5 , wherein the support substrate and the semiconductor chip substrate are different from each other in at least either size or shape. 7. The method for producing a semiconductor apparatus according to claim 5 , wherein the plurality of semiconductor chips include a plurality of semiconductor chips that are different in at least either plan view dimensions or thickness. 8. The method for producing a semiconductor apparatus according to claim 5 , wherein the plurality of semiconductor chips in which the second main face is bonded to the second support substrate are collectively bonded to the first support substrate in the bonding process. 9. The method for producing a semiconductor apparatus according to claim 5 , comprising a process of forming a groove on the support substrate along a dicing line at a time of cutting the joined wafer before bonding the semiconductor circuit sections. 10. The method for producing a semiconductor apparatus according to claim 5 , comprising a process of patterning the adhesive layer, wherein the semiconductor chips are bonded to the support substrate via the patterned adhesive layer. 11. The method for producing a semiconductor apparatus according to claim wherein the semiconductor circuit sections are light receiving sections of a solid-state image pickup device; and the support substrate and the adhesive layer are transparent.
by a substrate and the encapsulations · CPC title
Package configurations · CPC title
Circuitry of solid-state image sensors [SSIS]; Control thereof · CPC title
Microlenses · CPC title
Optical elements or arrangements associated with the image sensors · CPC title
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