Semiconductor memory device structure

Patent metadata

Field	Value
Publication number	US-11742307-B2
Application number	US-202217590592-A
Country	US
Kind code	B2
Filing date	Feb 1, 2022
Priority date	Jul 30, 2004
Publication date	Aug 29, 2023
Grant date	Aug 29, 2023

Abstract

A front-end method of fabricating nickel plated caps over copper bond pads used in a memory device. The method provides protection of the bond pads from an oxidizing atmosphere without exposing sensitive structures in the memory device to the copper during fabrication.

First claim

The invention claimed is:

1. A circuit, comprising:
a memory device including a transistor;
a bond pad over the transistor;
an insulating layer over the bond pad;
a substrate in electronic communication with the bond pad, wherein the substrate is in electronic communication with the bond pad via a bond wire; and
an array of memory cells over the insulating layer, the array of memory cells in electronic communication with the substrate.

2. The circuit of claim 1 , further comprising:
an electrode layer formed over the array of memory cells, wherein the electrode layer comprises tungsten, tantalum, or a combination thereof.

3. The circuit of claim 1 , wherein one of the memory cells comprises a resistance variable cell material.

4. A circuit, comprising:
a memory device including a transistor;
a bond pad over the transistor;
an insulating layer over the bond pad;
a substrate in electronic communication with the bond pad; and
an array of memory cells over the insulating layer the array of memory cells in electronic communication with the substrate, wherein the array of memory cells are in electronic communication with the substrate via a lead wire.

5. The circuit of claim 1 , further comprising:
a plurality of conductive traces in the insulating layer, wherein the plurality of conductive traces are insulated by a dielectric layer.

6. The circuit of claim 5 , further comprising:
a plurality of vias through the dielectric layer, wherein each of the plurality of vias is filled with a conductive material that is in electronic communication with the transistor.

7. The circuit of claim 5 , further comprising:
a first oxide layer over the dielectric layer; and
a nitride layer over the first oxide layer.

8. The circuit of claim 7 , further comprising:
a photoresist layer over the first oxide layer.

9. The circuit of claim 8 , further comprising:
a layer of resistance variable cell material over the photoresist layer; and
an electrode layer over the layer of resistance variable cell material, wherein the electrode layer comprises a plurality of layers of conductive material.

10. The circuit of claim 1 , wherein the substrate comprises a semiconductor material.

11. A method, comprising:
forming a transistor in contact with a substrate;
forming a first conductive layer over the transistor;
forming a bond pad in the first conductive laver, wherein the bond pad is in electronic communication with the transistor;
forming an insulating layer over the first conductive layer; and
forming a plurality of memory cells over the insulating layer.

12. The method of claim 11 , further comprising:
forming a plurality of conductive traces in the insulating layer, wherein the plurality of conductive traces are insulated by a dielectric layer.

13. The method of claim 12 , further comprising:
forming a plurality of vias through the dielectric layer, wherein each of the plurality of vias is filled with a conductive material that is in electronic communication with the transistor.

14. The method of claim 12 , further comprising:
forming a first oxide layer over the dielectric layer; and
forming a nitride layer over the first oxide layer.

15. The method of claim 14 , further comprising:
forming a photoresist layer over the first oxide layer.

16. The method of claim 15 , further comprising:
forming a layer of resistance variable cell material over the photoresist layer; and
forming an electrode layer over the layer of resistance variable cell material, wherein the electrode layer comprises a plurality of layers of conductive material.

17. The method of claim 11 , wherein the substrate comprises a semiconductor material.

18. The method of claim 11 , wherein forming the insulating layer comprises:
forming a first insulating layer over the first conductive layer; and
forming at least a second insulating layer over the first insulating layer.

Assignees

• Ovonyx Memory Tech Llc

Inventors

• Moore John
• Brooks Joseph F

Classifications

• H10W72/9445

  Top-view layouts, e.g. mirror arrays · CPC title

• H10W72/952

  comprising metals or metalloids, e.g. PbSn, Ag or Cu · CPC title

• H10W72/932

  Plan-view shape, i.e. in top view · CPC title

• H10W72/931

  Shapes of bond pads · CPC title

• H10W72/923

  Bond pads having multiple stacked layers · CPC title