Apparatus and methods to provide power management for memory devices

Patent metadata

Field	Value
Publication number	US-10074405-B2
Application number	US-201715633316-A
Country	US
Kind code	B2
Filing date	Jun 26, 2017
Priority date	Sep 6, 2012
Publication date	Sep 11, 2018
Grant date	Sep 11, 2018

Abstract

An apparatus, such as a nonvolatile solid-state memory device, may, in some implementations, include access line bias circuitry to set a bias level associated with a deselected access line(s) of a memory core in response to mode information. In one approach, access line bias circuitry may use linear down regulation to change a voltage level on deselected access lines of a memory core. A memory access device, such as a host processor, may be provided that is capable of dynamically setting a mode of operation of a memory core of a memory device in order to manage power consumption of the memory. Other apparatuses and methods are also provided.

First claim

The invention claimed is:

1. A method, comprising:
operating a memory device in a low-power mode, the memory device configured to operate in the low-power mode and a low-latency mode different than the low-power mode;
determining a bias level of a word line of the memory device based at least in part on the memory device operating in the low-power mode; and
accessing a memory cell of the memory device based at least in part on the bias level.

2. The method of claim 1 , further comprising:
determining an information transfer parameter associated with the memory cell of the memory device, wherein operating in the low-power mode is based at least in part on the information transfer parameter.

3. The method of claim 1 , further comprising:
determining whether a predicted number of write operations performed by the memory device satisfies a threshold, wherein operating in the low-power mode is based at least in part on the predicted number of write operations satisfying the threshold.

4. The method of claim 1 , further comprising:
initiating operation of the memory device in the low-latency mode based at least in part on an amount of power consumed by the memory device, an amount of latency in one or more access operations, a number of memory cells in the memory device, or a combination thereof.

5. The method of claim 1 , wherein:
the low-power mode is a read-only mode; and
the low-latency mode is a read/write mode.

6. The method of claim 1 , further comprising:
identifying data to be written to the memory cell of the memory device;
determining that the low-power mode that the memory device is operating in is a read-only mode;
initiating operation of memory device in the low-latency mode; and
writing the identified data to the memory cell while the memory device is operating in the low-latency mode.

7. The method of claim 1 , further comprising:
determining a bias level of a deselected word line of the memory device based at least in part on operating the memory device in the low-power mode, wherein accessing the memory cell is based at least in part on the bias level of the deselected word line.

8. The method of claim 1 , further comprising:
enabling an overlay window based at least in part on determining the bias level, wherein the overlay window is configured to control the bias level of the word line associated with the memory cell.

9. The method of claim 8 , further comprising:
writing information to a register of a command interface based at least in part on the overlay window, wherein enabling the overlay window is based at least in part writing the information to the register.

10. The method of claim 1 , further comprising:
controlling the bias level of the word line using a linear down regulator based at least in part on determining the bias level.

11. A method, comprising:
operating, by a memory device, in a low-power mode using a first bias level of a word line of the memory device;
determining an information transfer parameter associated with a memory cell of the memory device; and
initiating operation of the memory device in a low-latency mode different from the low-power mode based at least in part on determining the information transfer parameter.

12. The method of claim 11 , further comprising:
determining a second bias level of the word line of the memory device based at least in part on operating in the low-latency mode, the second bias level being different than the first bias level.

13. The method of claim 12 , further comprising:
accessing the memory cell of the memory device based at least in part on the second bias level associated with the low-latency mode.

14. The method of claim 11 , wherein determining the information transfer parameter further comprises:
determining that a predicted number of write operations of the memory device satisfies a threshold, wherein initiating the low-latency mode is based at least in part on the predicted number of write operations satisfying the threshold.

15. A method, comprising:
operating, by a memory device, in a low-power mode;
determining a first bias level of a word line of the memory device based at least in part on operating in the low-power mode, the first bias level being less than a second bias level associated with a low-latency mode of the memory device; and
determining a logic state stored on a memory cell of the memory device using the first bias level.

16. The method of claim 15 , further comprising:
applying the first bias level to the word line during a read operation, wherein determining the logic state is based at least in part on applying the first bias level.

17. The method of claim 15 , further comprising:
enabling an overlay window based at least in part on operating in the low-power mode, wherein the overlay window is configured to control a bias level of the word line associated with the memory cell during an access operation.

18. The method of claim 15 , further comprising:
activating a linear down regulator based at least in part on operating in the low-power mode, wherein the linear down regulator is configured to generate the first bias level by reducing a voltage level associated with the second bias level.

Assignees

• Ovonyx Memory Tech Llc

Inventors

• Barkley Gerald
• Hendrickson Nicholas

Classifications

• G11C5/147 Primary

  Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops (G11C5/141 takes precedence) · CPC title

• G11C7/1015

  Read-write modes for single port memories, i.e. having either a random port or a serial port · CPC title

• G11C5/14 Primary

  Power supply arrangements {, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels} · CPC title

• G11C16/3427

  Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written · CPC title

• G11C16/30

  Power supply circuits · CPC title