Semiconductor memory device structure

Patent metadata

Field	Value
Publication number	US-9966349-B2
Application number	US-201715412873-A
Country	US
Kind code	B2
Filing date	Jan 23, 2017
Priority date	Jul 30, 2004
Publication date	May 8, 2018
Grant date	May 8, 2018

Abstract

A semiconductor memory device and front-end method of fabricating nickel plated caps over bond pads used in a memory device. The method provides protection of the bond pads from an oxidizing atmosphere without exposing sensitive structures in the memory device to the copper during fabrication. In some examples, the method and device include one or more conductive and insulating layers formed over a substrate, and a plurality of memory cells over the conductive and insulating layers.

First claim

The invention claimed is:

1. An integrated circuit, comprising:
a memory device including a plurality of transistors;
a conductive bond pad over the plurality of transistors;
a first insulating layer over the conductive bond pad;
a second insulating layer over the first insulating layer;
a substrate in electronic communication with the conductive bond pad via a bond wire; and
an array of memory cells over the second insulating layer, the array of memory cells in electronic communication with the substrate via a lead wire.

2. The integrated circuit of claim 1 , further comprising:
an electrode layer formed over the array of memory cells, wherein the electrode layer comprises tungsten, tantalum, or a combination thereof.

3. The integrated circuit of claim 1 , wherein one of the memory cells comprises a resistance variable cell material.

4. The integrated circuit of claim 1 , further comprising:
a plurality of conductive traces in the second insulating layer, wherein the plurality of conductive traces are insulated by an interlevel dielectric (ILD) layer.

5. The integrated circuit of claim 4 , further comprising:
a plurality of vias through the ILD layer, wherein each of the plurality of vias is filled with a conductive material that is in electronic communication with one of the plurality of transistors.

6. The integrated circuit of claim 4 , further comprising:
a first oxide layer over the ILD layer; and
a nitride layer over the first oxide layer.

7. The integrated circuit of claim 6 , further comprising:
a photoresist layer over the first oxide layer.

8. The integrated circuit of claim 7 , further comprising:
a layer of resistance variable cell material over the photoresist layer; and
an electrode layer over the layer of resistance variable cell material, wherein the electrode layer comprises a plurality of layers of conductive material.

9. The integrated circuit of claim 1 , wherein the substrate comprises a semiconductor material.

10. A method, comprising:
forming a plurality of transistors in contact with a substrate;
forming a first conductive layer over the plurality of transistors;
forming a first insulating layer over the first conductive layer;
forming a second insulating layer over the first insulating layer; and
forming a plurality of memory cells over the second insulating layer.

11. The method of claim 10 , further comprising:
forming a conductive bond pad in the first conductive layer, wherein the conductive bond pad is in electronic communication with the plurality of transistors.

12. The method of claim 10 , further comprising:
forming a plurality of conductive traces in the second insulating layer, wherein the plurality of conductive traces are insulated by an interlevel dielectric (ILD) layer.

13. The method of claim 12 , further comprising:
forming a plurality of vias through the ILD layer, wherein each of the plurality of vias is filled with a conductive material that is in electronic communication with one of the plurality of transistors.

14. The method of claim 12 , further comprising:
forming a first oxide layer over the ILD layer; and
forming a nitride layer over the first oxide layer.

15. The method of claim 14 , further comprising:
forming a photoresist layer over the first oxide layer.

16. The method of claim 15 , further comprising:
forming a layer of resistance variable cell material over the photoresist layer; and
forming an electrode layer over the layer of resistance variable cell material, wherein the electrode layer comprises a plurality of layers of conductive material.

17. The method of claim 10 , wherein the substrate comprises a semiconductor material.

Assignees

• Ovonyx Memory Tech Llc

Inventors

• Moore John
• Brooks Joseph F

Classifications

• H10W72/9445

  Top-view layouts, e.g. mirror arrays · CPC title

• H10W72/952

  comprising metals or metalloids, e.g. PbSn, Ag or Cu · CPC title

• H10W72/932

  Plan-view shape, i.e. in top view · CPC title

• H10W72/931

  Shapes of bond pads · CPC title

• H10W72/923

  Bond pads having multiple stacked layers · CPC title