Apparatus and methods to provide power management for memory devices

Patent metadata

Field	Value
Publication number	US-9711191-B2
Application number	US-201514703668-A
Country	US
Kind code	B2
Filing date	May 4, 2015
Priority date	Sep 6, 2012
Publication date	Jul 18, 2017
Grant date	Jul 18, 2017

Abstract

An apparatus, such as a nonvolatile solid-state memory device, may, in some implementations, include access line bias circuitry to set a bias level associated with a deselected access line(s) of a memory core in response to mode information. In one approach, access line bias circuitry may use linear down regulation to change a voltage level on deselected access lines of a memory core. A memory access device, such as a host processor, may be provided that is capable of dynamically setting a mode of operation of a memory core of a memory device in order to manage power consumption of the memory. Other apparatuses and methods are also provided.

First claim

We claim:

1. A system comprising:
a processor; and
a non-volatile memory, wherein the non-volatile memory comprises:
a memory core;
a word line bias circuit configured to provide the memory core with an adjustable bias; and
an overlay window configured to control a bias level provided by a word line bit, wherein the bias level is selected based on a mode, wherein a first bias level is selected for a lower latency read/write mode and a second bias level is selected for a lower-power read mode.

2. The system of claim 1 , wherein the non-volatile memory further comprises:
a first operational amplifier having a non-inverting input, an inverting input, and an output, wherein the non-inverting input is configured to receive a first reference voltage;
a first N-type insulated-gate field effect transistor (IGFET) having a gate, a drain, and a source, wherein the gate of the first N-type IGFET is coupled to the output of the first operational amplifier;
a first voltage divider having a first end, a second end, and at least one tap, wherein the first end is coupled to the source of the first N-type IGFET and the at least one tap is coupled to the inverting input of the first operational amplifier;
a first buffer amplifier having an input and an output, wherein the input is coupled to the gate of the first N-type IGFET;
a second buffer amplifier having an input and an output, wherein the input is coupled to the source of the first N-type IGFET;
a second N-type IGFET having a gate, a drain, and a source, wherein the gate of the second N-type IGFET is operatively coupled to the output of the first buffer amplifier in a first mode; and
a P-type IGFET having a gate, a drain, and a source, wherein the gate of the P-type IGFET is operatively coupled to the output of the second buffer amplifier in the first mode, wherein the source of the P-type IGFET is coupled to the source of the second N-type IGFET and to an output node, wherein the output node is configured to provide a bias for a memory access line.

3. The system of claim 2 , further comprising a capacitor having an end coupled to the gate of the second N-type IGFET.

4. The system of claim 2 , wherein the voltage divider comprises a plurality of taps of different voltage levels, wherein the at least one tap is selected from the plurality of taps during production.

5. The system of claim 2 , wherein at least one resistor of the voltage divider is laser trimmed during production.

6. The system of claim 2 , further comprising an enable switch coupled to a drain of the first N-type IGFET.

7. The system of claim 2 , further comprising
a second operational amplifier having a non-inverting input, an inverting input, and an output, wherein the non-inverting input is configured to receive a second reference voltage;
a third N-type IGFET having a gate, a drain, and a source, wherein the gate of the third N-type IGFET is coupled to the output of the second operational amplifier;
a second voltage divider having a first end, a second end, and at least one tap, wherein the first end is coupled to the source of the third N-type IGFET and the at least one tap is coupled to the inverting input of the second operational amplifier;
a third buffer amplifier having an input and an output, wherein the input is coupled to the gate of the third N-type IGFET; and
a fourth buffer amplifier having an input and an output, wherein the input is coupled to the source of the third N-type IGFET;
wherein the gate of the second N-type IGFET is operatively coupled to the output of the third buffer amplifier in a second mode;
wherein the gate of the P-type IGFET is operatively coupled to the output of the fourth buffer amplifier in the second mode.

8. The system of claim 7 , further comprising:
a first switch disposed in a signal path between the output of the first buffer amplifier and the gate of the second N-type IGFET;
a second switch disposed in a signal path between the output of the second buffer amplifier and the gate of the second N-type IGFET;
a third switch disposed in a signal path between the output of the third buffer amplifier and the gate of the P-type IGFET; and
a fourth switch disposed in a signal path between the output of the fourth buffer amplifier and the gate of the P-type IGFET.

Assignees

• Ovonyx Memory Tech Llc

Inventors

• Barkley Gerald
• Hendrickson Nicholas

Classifications

• G11C5/147 Primary

  Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops (G11C5/141 takes precedence) · CPC title

• G11C7/1015

  Read-write modes for single port memories, i.e. having either a random port or a serial port · CPC title

• G11C5/14 Primary

  Power supply arrangements {, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels} · CPC title

• G11C16/3427

  Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written · CPC title

• G11C16/30

  Power supply circuits · CPC title