Issuing instructions on a vector processor

Patent metadata

Field	Value
Publication number	US-11741044-B2
Application number	US-202117566460-A
Country	US
Kind code	B2
Filing date	Dec 30, 2021
Priority date	Dec 30, 2021
Publication date	Aug 29, 2023
Grant date	Aug 29, 2023

Abstract

The present disclosure relates to a mechanism for issuing instructions in a processor (e.g., a vector processor) implemented as an overlay on programmable hardware (e.g., a field programmable gate array (FPGA) device). Implementations described herein include features for optimizing resource availability on programmable hardware units and enabling superscalar execution when coupled with a temporal single-instruction multiple data (SIMD). Systems described herein involve an issue component of a processor controller (e.g., a vector processor controller) that enables fast and efficient instruction issue while verifying that structural and data hazards between instructions have been resolved.

First claim

What is claimed is:

1. A method being implemented by a processor as an overlay on programmable hardware, the method comprising:
receiving, by a control unit, an instruction for execution on a functional unit of the processor;
placing the instruction in an instruction issue queue, the instruction issue queue including a plurality of instructions received by the control unit, and wherein the instruction issue queue includes an indication of a range of instructions that have not been issued;
applying at least one hazard tracker to the instruction to determine a lack of resource availability for executing the instruction on the at least one functional unit, wherein the control unit attempts to issue the instruction prior to the at least one hazard tracker confirming availability for executing the instructions on the at least one functional unit; and
resetting, based on determining the lack of availability for executing the instruction on the at least one functional unit, at least one issued instruction and modifying the instruction issue queue based on an earliest instruction that has not successfully issued.

2. The method of claim 1 , wherein the programmable hardware is a field programmable gate array (FPGA) device.

3. The method of claim 2 , wherein the processor is a vector processor implemented as an overlay on the FPGA device.

4. The method of claim 1 , wherein the range of instructions includes:
a head pointer indicating a slot of an earliest instruction of the instruction issue queue that has not successfully issued; and
a tail pointer indicating a slot of a most recent instruction added to the instruction issue queue or a slot after the most recent instruction added to the instruction issue queue.

5. The method of claim 1 , wherein placing the instructions in the instruction issue queue and applying the at least one hazard tracker to the instructions are performed based on an assumption that the instruction will issue successfully.

6. The method of claim 1 , wherein applying the at least one hazard tracker comprises:
applying a first hazard tracker configured to verify structural availability for one or more of a register file or a functional unit; and
applying a second hazard tracker configured to verify data availability.

7. The method of claim 6 , wherein applying the at least one hazard tracker comprises:
identifying a latency of the at least one functional unit; and
causing one or more of the first hazard tracker and the second hazard tracker to initiate checking for an associated hazard type based on the identified latency of the at least one functional unit.

8. The method of claim 1 , wherein applying the at least one hazard comprises applying a register file hazard tracker to the instruction to determine whether data is available for the instruction to start executing.

9. The method of claim 1 , wherein applying the at least one hazard tracker comprises applying a functional unit occupancy hazard tracker to determine whether the at least one functional unit is available to execute the instruction.

10. The method of claim 1 , wherein applying the at least one hazard tracker comprises applying a write port arbiter hazard tracker to determine whether another functional unit is not writing to a same bank of a register file in the same cycle as the at least one functional unit.

11. The method of claim 1 , wherein the control unit is positioned between:
a scalar unit that provides expanded instructions to the control unit; and
a plurality of lanes having functional units thereon for executing the plurality of instructions.

12. The method of claim 1 , wherein applying the at least one hazard tracker comprises:
applying a first hazard tracker to the instruction, the first hazard tracker being a register file hazard tracker configured to determine whether data is available for the instruction to start executing;
applying a second hazard tracker to the instruction, the second hazard tracker being a functional unit occupancy hazard tracker configured to determine whether the at least one functional unit is available to execute the instruction;
applying a third hazard tracker to the instruction, the third hazard tracker being a write port arbiter hazard tracker configured to determine whether another functional unit is writing to a same register in the same cycle as the at least one functional unit.

13. The method of claim 12 , wherein the first hazard tracker, the second hazard tracker, and the third hazard tracker are applied to the instruction in parallel with one another.

14. A processor implemented as an overlay on programmable hardware, comprising:
a scalar unit configured to fetch and decode instructions;
a plurality of lanes comprising functional units thereon configured to execute instructions; and
a control unit being configured to:
receive, from the scalar unit, an instruction for execution on a functional unit of the processor;
place the instruction in an instruction issue queue, the instruction issue queue including a plurality of instructions received by the control unit, and wherein the instruction issue queue includes an indication of a range of instructions that have not been issued;
apply at least one hazard tracker to the instruction to determine a lack of resource availability for executing the instruction on the at least one functional unit, wherein the control unit attempts to issue the instruction prior to the at least one hazard tracker confirming availability for executing the instructions on the at least one functional unit; and
reset, based on determining the lack of availability for executing the instruction on the at least one functional unit, at least one issued instruction and modifying the instruction issue queue based on an earliest instruction that has not successfully issued.

15. The processor of claim 14 , wherein the range of instructions includes:
a head pointer indicating a slot of an earliest instruction of the instruction issue queue that has not successfully issued; and
a tail pointer indicating a slot of a most recent instruction added to the instruction issue queue or a slot after the most recent instruction added to the instruction issue queue.

16. The processor of claim 14 , wherein the control unit is further configured to place the instructions in the instruction issue queue and apply the at least one hazard tracker to the instructions based on an assumption that the instruction will issue successfully.

17. The processor of claim 14 , wherein applying the at least one hazard comprises applying a register file hazard tracker to the instruction to determine whether data is available for the instruction to start executing.

18. The processor of claim 14 , wherein applying the at least one hazard tracker comprises applying a functional unit occupancy hazard tracker to determine whether the at least one functional unit is available to execute the instruction.

19. The processor of claim 14 , wherein applying the at least one hazard tracker comprises applying a write port arbiter hazard tracker to determine whether another functional unit is writing to a same register in the same cycle as the at least one functional unit.

20. The processor of claim 14 , wherein applying the at least one hazard tracker comprises:
applying a first hazard tracker to the instruction, the first hazard tracker being a register file hazard tracker configured to determine whether data is available for the instruction to start executing;
applying a second hazard tracker

Assignees

• Microsoft Technology Licensing Llc

Inventors

• Landy Aaron Michael
• Hurkat Skand

Classifications

• G06F15/8053 Primary

  Vector processors · CPC title

• G06F2015/768

  Gate array · CPC title

• G06F9/3838 Primary

  Dependency mechanisms, e.g. register scoreboarding · CPC title

• G06F9/30141

  Implementation provisions of register files, e.g. ports · CPC title

• G06F9/3861

  Recovery, e.g. branch miss-prediction, exception handling (error detection or correction G06F11/00) · CPC title