Data processing

Patent metadata

Field	Value
Publication number	US-10445093-B2
Application number	US-201615371670-A
Country	US
Kind code	B2
Filing date	Dec 7, 2016
Priority date	Dec 10, 2015
Publication date	Oct 15, 2019
Grant date	Oct 15, 2019

Abstract

Data processing apparatus comprises vector processing circuitry to apply a vector processing instruction to data vectors having a data vector length, each data vector comprising a plurality of data items equal in number to the data vector length, the vector processing circuitry having circuitry defining a plurality of processing lanes, there being at least as many processing lanes as a maximum data vector length; and control circuitry to selectively vary the data vector length used by the vector processing circuitry amongst a plurality of possible data vector length values up to the maximum data vector length and to disable operation of a subset of the processing lanes so that the disabled subset of processing lanes are unavailable for use by the vector processing circuitry and there remain at least as many enabled processing lanes as the data vector length set by the control circuitry.

First claim

We claim:

1. Data processing apparatus comprising:
vector processing circuitry to apply a vector processing instruction to data vectors having a data vector length, each data vector comprising a plurality of data items equal in number to the data vector length, the vector processing circuitry having circuitry defining a plurality of processing lanes, there being at least as many processing lanes as a maximum data vector length; and
control circuitry to selectively vary the data vector length used by the vector processing circuitry amongst a plurality of possible data vector length values up to the maximum data vector length and to disable operation of a subset of the processing lanes so that the disabled subset of processing lanes are unavailable for use by the vector processing circuitry and there remain at least as many enabled processing lanes as the data vector length set by the control circuitry;
wherein the vector processing circuitry comprises an instruction decoder to decode vector processing instructions into sets of operations, the number of sets being equal to the data vector length set by the control circuitry, and
wherein the control circuitry is configured to temporarily inhibit the decoding of vector processing instructions in response to an operation to increase the data vector length and to allow continued decoding of vector processing instructions in response to an operation to reduce the data vector length.

2. Apparatus according to claim 1 , in which the control circuitry is configured to disable a power supply to the subset of processing lanes.

3. Apparatus according to claim 1 , in which:
the vector processing circuitry comprises one or more data structures to store information on the sets of operations; and
the control circuitry is configured to selectively disable operation of a portion of the one or more data structures in dependence upon the data vector length set by the control circuitry.

4. Apparatus according to claim 1 , in which:
each processing lane comprises one or more data registers;
the vector processing circuitry is configured to load data from a memory into the data registers and to write data from the registers to the memory; and
the control circuitry is configured to inhibit the vector processing circuitry from writing data to the memory from data registers corresponding to the subset of processing lanes.

5. Apparatus according to claim 4 , in which the control circuitry is configured to inhibit the vector processing circuitry from altering data values held by data registers corresponding to the subset of processing lanes.

6. Apparatus according to claim 5 , in which the control circuitry is configured to maintain data values held by data registers corresponding to the subset of processing lanes.

7. Apparatus according to claim 1 , in which the control circuitry is responsive to a set-length instruction to set a data vector length.

8. Apparatus according to claim 7 , in which the control circuitry is configured to temporarily enable all of the processing lanes during one or both of decoding and execution of a set-length instruction, and then to disable the subset of the processing lanes so that there remain as many enabled processing lanes as the data vector length.

9. Apparatus according to claim 7 , in which:
the apparatus is operable in a plurality of security modes such that instructions executed in a lower security mode cannot access data items accessible by instructions executed in a higher security mode; and
the control circuitry is responsive to decoding of the set-length instruction in a current security mode to set the data vector length applicable to a lower security mode.

10. Apparatus according to claim 9 , in which the control circuitry is responsive to decoding of the set-length instruction in the current security mode to set the data vector length applicable to the lower security mode to a data vector length no greater than the data vector length currently applicable to the current security mode.

11. Apparatus according to claim 7 , in which the set-length instruction is dependent upon an operand selected from the list consisting of:
(i) an operand defining an absolute vector length value; and
(ii) an operand defining a proportion of the maximum data vector length.

12. Apparatus according to claim 1 , in which:
the apparatus is configured to execute a set of instructions multiple times; and
the control circuitry is configured to set a data vector length in response to one or more parameters of the processing of the set of instructions.

13. Data processing apparatus comprising:
vector processing means for applying a vector processing instruction to data vectors having a data vector length, each data vector comprising a plurality of data items equal in number to the data vector length, the vector processing means having means defining a plurality of processing lanes, there being at least as many processing lanes as a maximum data vector length; and
control means for selectively varying the data vector length used by the vector processing circuitry amongst a plurality of possible data vector length values up to the maximum data vector length;
the control means being operable to disable operation of a subset of the processing lanes so that the disabled subset of processing lanes are unavailable for use by the vector processing means and there remain at least as many enabled processing lanes as the data vector length set by the control means;
wherein the vector processing means comprises an instruction decoding means for decoding vector processing instructions into sets of operations, the number of sets being equal to the data vector length set by the control circuitry, and
wherein the control means is operable to temporarily inhibit the decoding of vector processing instructions in response to an operation to increase the data vector length and to allow continued decoding of vector processing instructions in response to an operation to reduce the data vector length.

14. A data processing method comprising:
applying a vector processing instruction to data vectors having a data vector length, each data vector comprising a plurality of data items equal in number to the data vector length, using circuitry defining a plurality of processing lanes, there being at least as many processing lanes as a maximum data vector length;
selectively varying the data vector length used by the vector processing circuitry amongst a plurality of possible data vector length values up to the maximum data vector length, by disabling operation of a subset of the processing lanes so that the disabled subset of processing lanes are unavailable for use by the vector processing circuitry and there remain at least as many enabled processing lanes as the data vector length set by the control circuitry;
wherein the applying a vector processing instruction to data vectors comprises decoding vector processing instructions into sets of operations, the number of sets being equal to the data vector length set by the control circuitry, and
the method further comprising temporarily inhibiting the decoding of vector processing instructions in response to an operation to increase the data vector length and allowing continued decoding of vector processing instructions in response to an operation to reduce the data vector length.

Assignees

• Advanced Risc Mach Ltd

Inventors

• Eyole Mbou
• Boettcher Matthias Lothar

Classifications

• G06F9/3814

  Implementation provisions of instruction buffers, e.g. prefetch buffer; banks · CPC title

• G06F9/3016

  Decoding the operand specifier, e.g. specifier format · CPC title

• G06F9/30189

  according to execution mode, e.g. mode flag · CPC title

• G06F15/8053 Primary

  Vector processors · CPC title

• G06F9/30076

  to perform miscellaneous control operations, e.g. NOP · CPC title