Address and control signal training

Patent metadata

Field	Value
Publication number	US-2016172013-A1
Application number	US-201414566265-A
Country	US
Kind code	A1
Filing date	Dec 10, 2014
Priority date	Dec 10, 2014
Publication date	Jun 16, 2016
Grant date	—

Abstract

In one form, an apparatus comprises a delay circuit and a controller. The delay circuit delays a plurality of command and address signals according to a first delay signal and provides a delayed command and address signal to memory interface. The controller performs command and address training in which the controller provides an activation signal and a predetermined address signal with first timing according to the first delay signal, and the plurality of command and address signals besides the predetermined address signal with second timing according to the first delay signal, wherein the second timing is relaxed with respect to the first timing. The controller determines an eye of timing for the predetermined address signal by repetitively providing a predetermined command on the command and address signals, varying the first delay signal, and measuring a data signal received from the memory interface.

First claim

What is claimed is:

1 . An apparatus comprising:
a delay circuit for delaying a plurality of command and address signals according to a first delay signal and providing a plurality of delayed command and address signals to a memory interface; and a controller for performing command and address training in which said controller provides an activation signal and a predetermined address signal with first timing according to said first delay signal, and said plurality of command and address signals besides said predetermined address signal with second timing, wherein said second timing is relaxed with respect to said first timing, and said controller determines an eye of timing for said predetermined address signal by repetitively providing a predetermined command on said command and address signals, varying said first delay signal, and measuring a data signal received from said memory interface.

2 . The apparatus of claim 1 wherein said first timing comprises being valid for one period of a clock signal and said second timing comprises being valid for two periods of said clock signal.

3 . The apparatus of claim 1 wherein said controller performs said command and address training in a training mode, and provides said plurality of command and address signals besides said predetermined address signal with said first timing according to a selected variable delay to said memory interface in a normal operation mode.

4 . The apparatus of claim 1 wherein said predetermined command comprises a multi-purpose register read command of a double data rate version four (DDR4) memory.

5 . The apparatus of claim 1 wherein said controller measures said data signal received from said memory interface by observing said data signal at two points in time.

6 . The apparatus of claim 1 wherein said activation signal comprises a chip select signal.

7 . An apparatus comprising:
a memory interface; a data processor for generating memory access requests during a normal operation mode and providing said memory access requests to said memory interface using a memory access controller; and a memory system coupled to said memory interface for receiving and responding to said memory access requests, wherein in a training mode, said memory access controller performs command and address training by providing an activation signal and a predetermined address signal with first timing according to a first delay signal, and a plurality of command and address signals besides said predetermined address signal with second timing, wherein said second timing is relaxed with respect to said first timing, and said memory access controller determines an eye of timing for said activation signal by repetitively providing a predetermined command on said command and address signals, varying said first delay signal, and measuring a data signal received from said memory interface.

8 . The apparatus of claim 7 wherein said first timing comprises being valid for one period of a clock signal and said second timing comprises being valid for two periods of said clock signal.

9 . The apparatus of claim 7 wherein said memory access controller performs said command and address training in said training mode, and provides said plurality of command and address signals besides said predetermined address signal with said first timing according to a selected variable delay to said memory interface in said normal operation mode.

10 . The apparatus of claim 7 wherein said predetermined command comprises a multi-purpose register read command.

11 . The apparatus of claim 10 wherein said memory system comprises double data rate version four (DDR4) memory.

12 . The apparatus of claim 7 wherein said memory access controller measures said data signal received from said memory interface by observing said data signal at two points in time.

13 . The apparatus of claim 12 wherein said memory access controller further delays a clock signal according to a second delay and performs write levelization to determine said second delay during said training mode.

14 . The apparatus of claim 13 wherein said memory access controller further performs two-dimensional training to find a data eye of a receive data strobe delay signal and a transmit data delay signal.

15 . The apparatus of claim 14 wherein said memory access controller further performs said two-dimensional training subsequent to said command and address training.

16 . A method for training command and address signals to be provided on a memory interface comprising:
for each of a plurality of values of a first delay signal:
issuing a read command to the memory interface by providing an activation signal with first timing based on a clock signal, and a selected address signal with said first timing and a plurality of command and additional address signals with second timing according to said first delay signal, wherein said second timing is relaxed with respect to said first timing; and
receiving a data feedback signal in response to said read command, and
setting said first delay signal to a selected variable delay corresponding to a data eye of a plurality of values of said feedback signal.

17 . The method of claim 16 further comprising:
setting said first delay signal to a start value before said issuing and said receiving for each of said plurality of values of said first delay signal.

18 . The method of claim 16 wherein:
the method further comprises for each of said plurality of values of said first delay signal, storing said data feedback signal in a table; and
wherein said setting comprises setting said first delay signal to said selected variable delay corresponding to said data eye of said plurality of values of said feedback signal using said table.

19 . The method of claim 18 wherein said issuing said read command to said memory comprises:
issuing a double data rate four (DDR4) multi-purpose register read command.

20 . The method of claim 16 wherein said issuing said read command to said memory interface further comprises:
receiving said activation signal from the memory interface; and
providing memory data to the memory interface in response to said activation signal and said read command.

Assignees

• Advanced Micro Devices Inc

Inventors

• Dearth Glenn
• Kashem Anwar
• Cummins Sean

Classifications

• G11C7/22

  Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management · CPC title

• G06F1/10 Primary

  Distribution of clock signals {, e.g. skew} · CPC title

• G06F13/1689 Primary

  Synchronisation and timing concerns (synchronisation on a memory bus G06F13/4234) · CPC title

• G06F13/00

  Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units (interface circuits for specific input/output devices G06F3/00 {; multiprogram control therefor  G06F9/46}; multiprocessor systems  G06F15/16 ) · CPC title

• G11C7/1072 Primary

  for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories · CPC title