Controller and semiconductor system including a controller

Patent metadata

Field	Value
Publication number	US-10692551-B2
Application number	US-201816206507-A
Country	US
Kind code	B2
Filing date	Nov 30, 2018
Priority date	May 18, 2018
Publication date	Jun 23, 2020
Grant date	Jun 23, 2020

Abstract

A controller configured to perform a training process of sampling data using multi-phase signals which are internally generated according to a data strobe signal, and compensating for a delay time of the data strobe signal using a control code which is generated according to the sampling result.

First claim

What is claimed is:

1. A semiconductor system comprising:
a semiconductor device configured to output a data and a data strobe signal according to a command; and
a controller configured to perform a training process of sampling the data using multi-phase signals and compensating for a delay time of the data strobe signal using a control code,
wherein the multi-phase signals are generated according to the data strobe signal by the controller, and
wherein the control code is generated according to the sampling result by the controller.

2. The semiconductor system according to claim 1 , wherein the controller performs a first edge matching operation for matching timing of a lead signal with timing of the data using a delay code as the control code, the delay code corresponding to any one delay code identified as the lead signal among delay codes corresponding to the respective multi-phase signals, as a part of the training process.

3. The semiconductor system according to claim 2 , wherein the controller performs a second edge matching operation for matching timing of a trail signal with timing of the data using a delay code as the control code, the delay code corresponding to any one delay code identified as the trail signal among the delay codes, as a part of the training process.

4. The semiconductor system according to claim 3 , wherein the controller generates a compensated data strobe signal by delaying the data strobe signal by a delay time corresponding to the control code corresponding to an intermediate value between the control code corresponding to the lead signal at which the first edge matching operation has been completed and the control code corresponding to the trail signal at which the second edge matching operation has been completed, and then completes the training process.

5. The memory system of claim 1 , wherein the controller comprises:
a sampling circuit configured to generate sampling signals by sampling the data according to the multi-phase signals, and output the sampling signals;
a detection circuit configured to generate lead flags and trail flags according to the sampling signals;
a training control circuit configured to generate the control code according to the lead flags and the trail flags; and
a multi-phase signal generation circuit configured to output some signals having a desired phase among delayed signals in a delay line for delaying the data strobe signal, as the multi-phase signals.

6. The semiconductor system according to claim 5 , wherein the sampling circuit comprises a plurality of flip-flops for sampling the data according to the respective multi-phase signals.

7. The semiconductor system according to claim 5 , wherein each of the lead flags and the trail flags defines whether the multi-phase signal in the same order as the corresponding flag among the multi-phase signals is a lead signal or trail signal.

8. The semiconductor system according to claim 7 , wherein the lead signal and the trail signal are phase signals having the closest transition timings to transition timings of the data, among the multi-phase signals.

9. The semiconductor system according to claim 8 , wherein the lead signal is the immediately previous phase signal of a phase signal having a rising edge that initially corresponds to a high-level period of the data, among the multi-phase signals.

10. The semiconductor system according to claim 8 , wherein the trail signal is a phase signal having a rising edge that lastly corresponds to a high-level period of the data, among the multi-phase signals.

11. The semiconductor system according to claim 5 , wherein the detection circuit comprises:
a plurality of flip-flops configured to receive the sampling signals and generate shifted sampling signals;
a plurality of first logic gates configured to invert the shifted sampling signals;
a plurality of second logic gates configured to perform a first logical operation on the sampling signals and outputs of the first logic gates;
a first shift register configured to generate the lead flags by shifting outputs of the plurality of second logic gates;
a plurality of third logic gates configured to perform a second logical operation on the sampling signals and the shifted sampling signals;
a plurality of fourth logic gates configured to perform a third logical operation on outputs of the plurality of third logic gates and the sampling signals; and
a second shift register configured to generate the trail flags by shifting outputs of the plurality of fourth logic gates.

12. The semiconductor system according to claim 5 , wherein the training control circuit stores delay codes corresponding to delay values of the respective multi-phase signals, and performs first and second edge matching operations for matching rising edges of a lead signal and a trail signal with rising and falling edges of the data, respectively, while varying some delay codes of the delay codes as the control code, the some delay codes corresponding to the lead signal and the trail signal of the multi-phase signals, respectively.

13. The semiconductor system according to claim 12 , wherein the training control circuit sets a value of the control code to a delay time of the multi-phase signal generation circuit, the value of the control code corresponding to an intermediate value between the control code corresponding to the lead signal at which the first edge matching operation has been completed and the control code corresponding to the trail signal at which the second edge matching operation has been completed.

14. The semiconductor system according to claim 5 , wherein the training control circuit comprises:
a register configured to store the delay codes; and
a control circuit configured to perform first and second edge matching operations for matching rising edges of a lead signal and a trail signal with rising and falling edges of the data, respectively, while varying some delay codes of the delay codes as the control code, the some delay codes corresponding to the lead signal and the trail signal of the multi-phase signals, respectively, and set a value of the control code to a delay time of the multi-phase signal generation circuit, the value of the control code corresponding to an intermediate value between the control code corresponding to the lead signal at which the first edge matching operation has been completed and the control code corresponding to the trail signal at which the second edge matching operation has been completed.

15. The semiconductor system according to claim 5 , wherein the multi-phase signal generation circuit generates a compensated data strobe signal by delaying the data strobe signal by a delay time which is varied according to the control code.

16. The semiconductor system according to claim 5 , wherein the multi-phase signal generation circuit comprises:
a delay line configured to output some signals having a desired phase among output signals of a plurality of unit delays as the multi-phase signals, delay the data strobe signal by a varied delay time according to a delay control signal, and output the delayed signal as a compensated data strobe signal;
a replica configured to delay the compensated data strobe signal by a preset delay time, and output the delayed signal as a feedback signal;
a phase detector configured to generate a phase detection signal by detecting a phase difference between the data strobe signal and the feedback signal; and
a delay controller configured to generate the delay control signal according to the phase detection signal or the control code.

Assignees

• Sk Hynix Inc

Inventors

• Hwang Minsoon

Classifications

• G11C7/222 Primary

  Clock generating, synchronizing or distributing circuits within memory device · CPC title

• G11C2207/2254

  Calibration · CPC title

• G11C29/028

  with adaption or trimming of parameters · CPC title

• G11C29/023

  in clock generator or timing circuitry · CPC title

• G11C29/022

  in I/O circuitry · CPC title