Dielectric-dielectric and metallization bonding via plasma activation and laser-induced heating

US11735689B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-11735689-B2
Application numberUS-202217751090-A
CountryUS
Kind codeB2
Filing dateMay 23, 2022
Priority dateJun 11, 2019
Publication dateAug 22, 2023
Grant dateAug 22, 2023

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  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

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Abstract

Official abstract text for this publication.

The invention is directed towards enhanced systems and methods for employing a pulsed photon (or EM energy) source, such as but not limited to a laser, to electrically couple, bond, and/or affix the electrical contacts of a semiconductor device to the electrical contacts of another semiconductor devices. Full or partial rows of LEDs are electrically coupled, bonded, and/or affixed to a backplane of a display device. The LEDs may be μLEDs. The pulsed photon source is employed to irradiate the LEDs with scanning photon pulses. The EM radiation is absorbed by either the surfaces, bulk, substrate, the electrical contacts of the LED, and/or electrical contacts of the backplane to generate thermal energy that induces the bonding between the electrical contacts of the LEDs' electrical contacts and backplane's electrical contacts. The temporal and spatial profiles of the photon pulses, as well as a pulsing frequency and a scanning frequency of the photon source, are selected to control for adverse thermal effects.

First claim

Opening claim text (preview).

What is claimed is: 1. A system for coupling a semiconductor device to a target substrate, wherein the semiconductor device includes a first surface and a first contact disposed on the first surface, the target substrate includes a second surface and a second contact, and the system comprises: a fabrication apparatus that: forms a first insulating layer on the first surface, wherein the first insulating layer covers a portion of the first surface and exposes a distal portion of the first contact; and forms a second insulating layer on the second surface that at least partially forms a recessed void on the second surface such that the second contact is at least partially disposed within the recessed void, wherein the second insulating layer covers a portion of the second surface and exposes a distal portion of the second contact; a plasma apparatus that: exposes the first insulating layer and the second insulating layer to a plasma that activates each of the first insulating layer and the second insulating layer; a pick and place head (PPH) that: positions the semiconductor device proximate to the target substrate to form a spatial alignment of the first contact with the second contact, wherein the activated first and second insulating layers are adjacent and opposed layers, and the exposed distal portion of the second contact is adjacent the exposed distal portion of the first contact; and applies a compressive force to at least one of the semiconductor device or the target substrate to form a mechanical coupling between the semiconductor device and the target substrate by chemically bonding the activated first insulating layer to the activated second insulating layer, wherein the compressive force deforms a shape of the second contact such that the deformed shape of the second contact at least partially fills the recessed void; and an electrical coupling apparatus that: forms an electrical coupling between the semiconductor device and the target substrate by electrically bonding the exposed distal portion of the second contact to the adjacent distal portion of the first contact via inducing thermal energy with associated thermal effects that are localized to the first and second contacts, wherein the mechanical coupling between the semiconductor device and the target substrate mechanically stabilizes the electrical coupling. 2. The system of claim 1 , wherein the semiconductor device is a light-emitting diode (LED) with feature sizes that are less than 100 micrometers (μm) and the target substrate is a backplane of a display device. 3. The system of claim 1 , wherein the electrical coupling apparatus includes a scanning laser source that induces the thermal energy. 4. The system of claim 1 , wherein the electrical coupling apparatus transmits a photon pulse that induces the thermal energy, the photon pulse has a temporal profile that is selected to control thermal effects associated with the thermal energy induced by the photon pulse, and the thermal energy electrically bonds the exposed distal portion of the second contact to the adjacent distal portion of the first contact. 5. The system of claim 1 , wherein a combination of the chemically bonded first insulating layer and second insulating layer substantially encapsulates the electrically bonded first contact and second contact and mitigates an electromigration process associated with the first contact and the second contact. 6. The system of claim 1 , wherein at least one of the first contact or the second contact comprises gold. 7. The system of claim 1 , wherein at least one of the first or second insulating layers is comprised of silicon dioxide. 8. The system of claim 1 , wherein the plasma planarizes the activated first insulating layer and the activated second insulating layer to enhance the chemical bonding of the activated first insulating layer and the activated second insulating layer. 9. The system of claim 1 , wherein at least a portion of the recessed void is disposed between a portion of the second insulating layer and the second contact. 10. The system of claim 1 , wherein the compressive force deforms a shape of the first contact. 11. The system of claim 1 , wherein positioning the semiconductor device proximate to the target substrate and forming the mechanical coupling between the semiconductor device and the target substrate are performed at room temperature and at atmospheric pressure. 12. The system of claim 1 , wherein the semiconductor device is a first pre-diced semiconductor die included in a first semiconductor wafer and the target substrate is a second pre-diced semiconductor die included in a second semiconductor wafer, and wherein positioning the semiconductor device proximate to the target substrate includes positioning the first semiconductor wafer proximate the second semiconductor wafer. 13. The system of claim 1 , wherein the induced thermal energy is induced by a photon pulse with a temporal profile that is selected to control thermal effects associated with the thermal energy, and wherein controlling the thermal effects includes localizing the thermal effects to the first and second contacts. 14. The system of claim 13 , wherein the photon pulse is transmitted by a pulsed photon beam that is scanned across at least one of the semiconductor device or the target substrate. 15. A display device, comprising: a semiconductor device that includes a first surface and a first contact disposed on the first surface; and a target substrate that includes a second surface and a second contact disposed on the second surface, and wherein the display device was assembled by a method comprising: forming a first insulating layer on the first surface, wherein the first insulating layer covers a portion of the first surface and exposes a distal portion of the first contact; forming a second insulating layer on the second surface, wherein the second insulating layer covers a portion of the second surface and exposes a distal portion of the second contact; exposing the first insulating layer and the second insulating layer to a plasma that activates each of the first insulating layer and the second insulating layer; positioning the semiconductor device proximate to the target substrate to form a spatial alignment of the first contact with the second contact, wherein the activated first and second insulating layers are adjacent and opposed layers, and the exposed distal portion of the second contact is adjacent the exposed distal portion of the first contact; forming a mechanical coupling between the semiconductor device and the target substrate by chemically bonding the activated first insulating layer to the activated second insulating layer; and forming an electrical coupling between the semiconductor device and the target substrate by electrically bonding the exposed distal portion of the second contact to the adjacent distal portion of the first contact via inducing thermal energy with associated thermal effects that are localized to the first and second contacts, wherein the mechanical coupling between the semiconductor device and the target substrate mechanically stabilizes the electrical coupling. 16. The display device of claim 15 , wherein the display device is included in a head-mounted device that is at least one of a virtual-reality device, an augmented-reality device, or a mixed-reality device. 17. The display device of claim 15 , wherein the semiconductor device is a micro light emitting diode (μLED) with feature sizes that are less than 100 micrometers (μm) and the target substra

Assignees

Inventors

Classifications

  • Subject matter not provided for in other groups of this subclass · CPC title

  • Means for storing or moving the material for the connector · CPC title

  • Means for applying energy, e.g. ovens or lasers · CPC title

  • on active surfaces of flip-chip devices, e.g. underfills · CPC title

  • Bond pads, in general · CPC title

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Frequently asked questions

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What does patent US11735689B2 cover?
The invention is directed towards enhanced systems and methods for employing a pulsed photon (or EM energy) source, such as but not limited to a laser, to electrically couple, bond, and/or affix the electrical contacts of a semiconductor device to the electrical contacts of another semiconductor devices. Full or partial rows of LEDs are electrically coupled, bonded, and/or affixed to a backplan…
Who is the assignee on this patent?
Facebook Tech Llc, Meta Platforms Tech Llc
What technology area does this patent fall under?
Primary CPC classification H10H20/01. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Aug 22 2023 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 12 related publications on this page (citations in our corpus or others sharing the same primary CPC).