Semiconductor device and method for fabricating the same

Patent metadata

Field	Value
Publication number	US-11735663-B2
Application number	US-202117565650-A
Country	US
Kind code	B2
Filing date	Dec 30, 2021
Priority date	Oct 1, 2019
Publication date	Aug 22, 2023
Grant date	Aug 22, 2023

Abstract

Example semiconductor devices and methods for fabricating a semiconductor device are disclosed. An example device may include a substrate, a first semiconductor pattern spaced apart from the substrate, a first antioxidant pattern extending along a bottom surface of the first semiconductor pattern and spaced apart from the substrate, and a field insulating film on the substrate. The insulating film may cover at least a part of a side wall of the first semiconductor pattern. The first antioxidant pattern may include a first semiconductor material film doped with a first impurity.

First claim

What is claimed is:

1. A semiconductor device comprising:
a substrate;
a protruding pattern protruding from the substrate;
a lower semiconductor pattern spaced apart from the protruding pattern in a first direction, and extending in a second direction intersecting the first direction;
a plurality of upper semiconductor patterns spaced apart from the lower semiconductor pattern in the first direction;
a gate electrode wrapping around the plurality of upper semiconductor patterns;
a first antioxidant pattern extending along a bottom surface of the lower semiconductor pattern and spaced apart from the substrate in the first direction, the first antioxidant pattern including a first semiconductor material film doped with a first impurity; and
a field insulating film on the substrate, the field insulating film covering at least a part of a side wall of the lower semiconductor pattern,
wherein a portion of field insulating film is disposed between the first antioxidant pattern and the protruding pattern.

2. The semiconductor device of claim 1 , wherein the field insulating film does not cover at least a part of a side wall of the plurality of upper semiconductor pattern.

3. The semiconductor device of claim 1 , further comprising:
a fin liner, wherein
the fin liner extends along at least a part of the side wall of the lower semiconductor pattern, and
the fin liner extends between the field insulating film and the lower semiconductor pattern.

4. The semiconductor device of claim 3 , wherein the fin liner is not disposed on a side wall of the plurality of upper semiconductor patterns.

5. The semiconductor device of claim 1 , wherein the first antioxidant pattern includes silicon, silicon germanium, or both silicon and silicon germanium.

6. The semiconductor device of claim 1 , wherein the first impurity includes at least one of oxygen(O), nitrogen(N), and carbon(C).

7. The semiconductor device of claim 1 , further comprising:
a second antioxidant pattern extending along an upper surface of the protruding pattern, wherein
the second antioxidant pattern is spaced apart from the first antioxidant pattern.

8. The semiconductor device of claim 1 , wherein
the field insulating film includes a filling insulating film and a stress insulating film,
the stress insulating film includes an oxide containing germanium, and
the stress insulating film is between the first antioxidant pattern and the protruding pattern.

9. The semiconductor device of claim 1 , the first antioxidant pattern includes a plurality of first sub-patterns and a plurality of second sub-patterns alternatively stacked,
the plurality of first sub-patterns are undoped, and
the plurality of second sub-patterns are doped.

10. A semiconductor device comprising:
a substrate;
a lower semiconductor pattern spaced apart from the substrate;
a plurality of upper semiconductor patterns spaced apart from the lower semiconductor pattern;
a gate electrode wrapping around the plurality of upper semiconductor patterns;
a field insulating film on the substrate and covering at least a part of a side wall of the lower semiconductor pattern, the field insulating film including a filling insulating film and a stress insulating film, the stress insulating film including an oxide containing germanium; and
a fin liner extending along at least a part of the side wall of the lower semiconductor pattern and extending between the field insulating film and the lower semiconductor pattern,
the fin liner being arranged so the fin liner is not in contact with the substrate.

11. The semiconductor device of claim 10 , wherein the field insulating film does not cover at least a part of a side wall of the plurality of upper semiconductor patterns.

12. The semiconductor device of claim 10 , wherein the fin liner is not disposed on a side wall of the plurality of upper semiconductor patterns.

13. The semiconductor device of claim 10 , further comprising:
a protruding pattern protruding from the substrate, wherein
the field insulating film covers the protruding pattern, and
a height of a lower surface of the fin liner is higher than a height of an uppermost part of the protruding pattern relative to an upper surface of the substrate.

14. The semiconductor device of claim 10 , wherein a height of a lower surface of the fin liner is the same as or lower than the height of a bottom surface of the lower semiconductor pattern relative to an upper surface of the substrate.

15. The semiconductor device of claim 10 , wherein the fin liner includes a silicon nitride film.

16. The semiconductor device of claim 10 , wherein the stress insulating film is between the lower semiconductor pattern and the substrate.

17. A semiconductor device comprising:
a substrate;
a protruding pattern protruding from the substrate;
a lower semiconductor pattern spaced apart from the protruding pattern in a first direction, and extending in a second direction intersecting the first direction;
a plurality of upper semiconductor patterns spaced apart from the lower semiconductor pattern in the first direction;
an antioxidant pattern contacting the lower semiconductor pattern and extending along a bottom surface of the lower semiconductor pattern, the antioxidant pattern extending between the protruding pattern and the lower semiconductor pattern, the antioxidant pattern including a first semiconductor material film undoped and a second semiconductor material film doped with a first impurity;
a field insulating film on the substrate, the field insulating film covering at least a part of a side wall of the lower semiconductor pattern,
a gate insulating film wrapping around the plurality of upper semiconductor patterns, and extending along an upper surface of the field insulating film in a third direction intersecting the first and the second direction;
a gate electrode extending in the third direction on the gate insulating film;
a capping pattern on the gate electrode; and
a fin liner extending along at least a part of a side wall of the lower semiconductor pattern between the field insulating film and the lower semiconductor pattern.

18. The semiconductor device of claim 17 , wherein
the first semiconductor material film and the second semiconductor material film include silicon, and
the first impurity includes at least of one of oxygen(O), nitrogen(N), and carbon(C).

19. The semiconductor device of claim 17 , wherein a height a lower surface of the fin liner is higher than a height of an uppermost part of the protruding pattern relative to an upper surface of the substrate.

20. The semiconductor device of claim 17 , wherein the field insulating film includes a filling insulating film and a stress insulating film,
the stress insulating film includes an oxide containing germanium, and
the stress insulating film is between the antioxidant pattern and the protruding pattern.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Jin Bum
• Kim Gyeom
• Kim Da Hye
• Kim Jae Mun
• Shin Il Gyou
• Lee Seung Hun
• Choi Kyung In

Classifications

• H10P14/6308

  of Group IV semiconductors · CPC title

• H10P14/3462

  Nanowires · CPC title

• H10P14/3411

  Silicon, silicon germanium or germanium · CPC title

• H10D30/791

  Arrangements for exerting mechanical stress on the crystal lattice of the channel regions · CPC title

• H10D30/65

  Lateral DMOS [LDMOS] FETs · CPC title