Bulk finFET with partial dielectric isolation featuring a punch-through stopping layer under the oxide

Patent metadata

Field	Value
Publication number	US-9385233-B2
Application number	US-201313927698-A
Country	US
Kind code	B2
Filing date	Jun 26, 2013
Priority date	Jun 26, 2013
Publication date	Jul 5, 2016
Grant date	Jul 5, 2016

Abstract

A bulk finFET with partial dielectric isolation is disclosed. The dielectric isolation is disposed underneath the channel, and essentially bounded by the channel, such that it does not extend laterally beyond the channel under the source and drain regions. This allows increased volume of SiGe source and drain stressor regions placed adjacent to the channel, allowing for a more strained channel, which improves carrier mobility. An N+ doped silicon region is disposed below the dielectric isolation and extends laterally beyond the channel and underneath the stressor source and drain regions, forming a reverse-biased p/n junction with the P+ doped source and drain SiGe stressor to minimize leakage currents from under the insulator.

First claim

What is claimed is:

1. A method of forming a semiconductor structure, comprising:
forming an N+ doped silicon layer on a semiconductor substrate;
forming an undoped SiGe layer on the N+ doped silicon layer;
forming a silicon channel layer on the undoped SiGe layer;
forming a plurality of fins by performing a fin etch on the semiconductor structure;
depositing an oxide layer on the semiconductor structure and in between each of the plurality of fins;
forming a thermally formed oxide region by performing an anneal on the semiconductor structure;
forming a gate on the semiconductor substrate;
performing an anisotropic etch into the semiconductor structure adjacent to the gate, and extending into the N+ doped silicon layer; and
forming P+ doped SiGe regions adjacent to the gate and thermally formed oxide region, and extending into the N+ doped silicon layer.

2. The method of claim 1 , wherein forming the undoped SiGe layer comprises forming a SiGe layer having a germanium concentration ranging from about 30 percent to about 70 percent.

3. The method of claim 1 , wherein forming the N+ doped silicon layer comprises forming an in situ doped epitaxial layer.

4. The method of claim 1 , wherein forming the N+ doped silicon layer comprises performing an ion implantation on the semiconductor substrate.

5. The method of claim 1 , wherein forming the P+ doped SiGe regions adjacent to the gate comprises forming P+ doped SiGe regions having a germanium concentration ranging from about 25 percent to about 100 percent.

6. The method of claim 1 , wherein performing the anisotropic etch into the semiconductor structure comprises performing a reactive ion etch.

7. The method of claim 1 , wherein performing the anneal on the semiconductor structure comprises performing the anneal at a temperature ranging from about 500 degrees Celsius to about 600 degrees Celsius in steam a environment.

8. The method of claim 1 , wherein performing the anneal on the semiconductor structure comprises performing the anneal for a time duration ranging from about 120 minutes to about 360 minutes.

9. A method of forming a semiconductor structure, comprising:
forming an N+ doped silicon layer on a semiconductor substrate;
forming an undoped SiGe layer on the N+ doped silicon layer;
forming a silicon channel layer on the undoped SiGe layer;
forming a plurality of fins by performing a fin etch on the semiconductor structure;
depositing an oxide layer on the semiconductor structure and in between each of the plurality of fins;
forming a thermally formed oxide region by performing an anneal on the semiconductor structure;
forming a gate on the semiconductor structure;
performing an anisotropic etch into the semiconductor structure adjacent to the gate, and extending into the N+ doped silicon layer;
forming P+ doped SiGe regions adjacent to the gate and thermally formed oxide region, and extending into the N+ doped silicon layer,
wherein forming the N+ doped silicon layer on the semiconductor substrate, forming the undoped SiGe layer on the N+ doped silicon layer, and forming the silicon channel layer on the undoped SiGe layer, are performed with an uninterrupted chemical vapor deposition process.

10. The method of claim 9 , wherein forming the N-doped silicon layer comprises forming an in situ doped epitaxial layer.

11. The method of claim 10 , wherein forming the in situ doped epitaxial layer comprises adding phosphorus dopants.

Assignees

• Globalfoundries Inc

Inventors

• Akarvardar Murat K
• Jacob Ajey P

Classifications

• H10P95/90

  Thermal treatments, e.g. annealing or sintering · CPC title

• H10P50/242

  of Group IV materials · CPC title

• H10P14/6308

  of Group IV semiconductors · CPC title

• H10W10/181

  Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers · CPC title

• H10W10/0126

  introducing electrical active impurities in local oxidation regions to create channel stoppers · CPC title