Semiconductor device including Fin- FET and manufacturing method thereof

Patent metadata

Field	Value
Publication number	US-9780214-B2
Application number	US-201414579708-A
Country	US
Kind code	B2
Filing date	Dec 22, 2014
Priority date	Dec 22, 2014
Publication date	Oct 3, 2017
Grant date	Oct 3, 2017

Abstract

A semiconductor device includes a first fin structure for a first fin field effect transistor (FET). The first fin structure includes a first base layer protruding from a substrate, a first intermediate layer disposed over the first base layer and a first channel layer disposed over the first intermediate layer. The first fin structure further includes a first protective layer made of a material that prevents an underlying layer from oxidation. The first channel layer is made of SiGe, the first intermediate layer includes a first semiconductor (e.g., SiGe) layer disposed over the first base layer and a second semiconductor layer (e.g., Si) disposed over the first semiconductor layer. The first protective layer covers side walls of the first base layer, side walls of the first semiconductor layer and side walls of the second semiconductor layer.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a fin structure for a fin field effect transistor (FET), the fin structure comprising a base layer protruding from a substrate, an intermediate layer disposed over the base layer and an upper layer disposed over the intermediate layer;
an isolation insulating layer disposed on the substrate; and
a protective layer made of a material that prevents an underlying layer from oxidizing, wherein:
the intermediate layer includes a first semiconductor layer disposed over the base layer,
the protective layer covers at least a sidewall of the first semiconductor layer,
the intermediate layer further includes a second semiconductor layer disposed over the first semiconductor layer,
the upper layer is a channel layer including SiGe,
the protective layer covers a part of sidewall of the second semiconductor layer and sidewalls of the base layer,
the protective layer does not cover a sidewall of the upper layer and is spaced apart from the channel layer, and
the base layer and the protective layer are embedded in the isolation insulating layer.

2. The semiconductor device of claim 1 , wherein a thickness of the protective layer is 1 to 10 nm.

3. The semiconductor device of claim 1 , wherein the protective layer is made of silicon nitride.

4. The semiconductor device of claim 1 , wherein the protective layer is spaced apart from the bottom of the opening by a distance of 2 to 20 nm.

5. A semiconductor device, comprising:
a first fin structure for a first fin field effect transistor (FET), the first fin structure comprising a first base layer protruding from a substrate, a first intermediate layer disposed over the first base layer and a first channel layer disposed over the first intermediate layer; and
a first protective layer made of a material that prevents an underlying layer from oxidizing;
a second fin structure for a second fin FET, the second fin structure comprising a second base layer protruding from the substrate, a second intermediate layer disposed over the second base layer and a second channel layer disposed over the second intermediate layer; and
a second protective layer covering a sidewall of the second base layer, a sidewall of the second intermediate layer and a sidewall of the second channel layer, wherein:
the first channel layer is made of SiGe,
the first intermediate layer includes a first semiconductor layer disposed over the first base layer and a second semiconductor layer disposed over the first semiconductor layer,
the first protective layer covers a sidewall of the first base layer, a sidewall of the first semiconductor layer and a sidewall of a part of the Si layer, and
the first protective layer is spaced apart from the first channel layer.

6. The semiconductor device of claim 5 , wherein a height of the first protective layer is smaller than a height of the second protective layer.

7. The semiconductor device of claim 5 , wherein a difference between a height of the first protective layer is substantially equal to a height of the second protective layer.

8. The semiconductor device of claim 5 , wherein a distance of the first protective layer covering the sidewall of a part of the second semiconductor layer is 1 to 10 nm.

9. The semiconductor device of claim 5 , wherein the first protective layer is spaced apart from the first channel layer by a distance of 2 to 20 nm.

10. The semiconductor device of claim 5 , wherein a width of the first channel layer is at most 40 nm.

11. The semiconductor device of claim 5 , further comprising:
a first gate dielectric layer disposed over the first channel layer and a first gate electrode disposed over the first dielectric layer; and
a second gate dielectric layer disposed over the second channel layer and a second gate electrode disposed over the second dielectric layer.

12. The semiconductor device of claim 11 , further comprising:
a first metal layer disposed between the first gate dielectric layer and the first gate electrode; and
a second metal layer disposed between the second gate dielectric layer and the second gate electrode.

13. The semiconductor device of claim 5 , wherein the sidewall of the second intermediate layer is covered by a SiGe oxide.

14. A semiconductor device, comprising:
a fin structure for a fin field effect transistor (FET), the fin structure comprising a base layer protruding from a substrate, a first semiconductor layer disposed over the base layer and a second semiconductor layer disposed over the first semiconductor layer; and
an isolation insulting layer disposed on the substrate;
a protective layer, wherein:
the first semiconductor layer has a different lattice constant from the base layer and the second semiconductor layer, and
the protective layer covers an entire sidewall of the first semiconductor layer, a sidewall of a bottom part of the second semiconductor layer and a sidewall of the base layer, and
the base layer and the protective layer are embedded in the isolation insulating layer.

15. The semiconductor device of claim 14 , wherein the first semiconductor layer is made of SiGe.

16. The semiconductor device of claim 14 , wherein the protective layer is made of silicon nitride.

17. The semiconductor device of claim 14 , wherein:
the second semiconductor layer includes a lower semiconductor layer disposed over the first semiconductor layer and an upper semiconductor layer disposed over the lower semiconductor layer, and
at least the lower semiconductor layer has a different lattice constant from the first semiconductor layer.

18. The semiconductor device of claim 14 , wherein:
a sidewall of the first semiconductor layer is covered by a SiGe oxide layer, and
the SiGe oxide layer is covered by the protective layer.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Huang Gin-Chen
• Hsu Tzu-Hsiang
• Hsu Chia-Jung
• Yang Feng-Cheng
• Tsai Teng-Chun

Classifications

• H10W10/011

  of isolation regions comprising dielectric materials · CPC title

• H10W10/10

  Isolation regions comprising dielectric materials · CPC title

• H01L29/511

  Electricity · mapped topic

• H01L29/6681

  Electricity · mapped topic

• H01L29/785 Primary

  Electricity · mapped topic