Method of forming FinFET channel

Patent metadata

Field	Value
Publication number	US-9711535-B2
Application number	US-201514658023-A
Country	US
Kind code	B2
Filing date	Mar 13, 2015
Priority date	Mar 13, 2015
Publication date	Jul 18, 2017
Grant date	Jul 18, 2017

Abstract

A method for fabricating a semiconductor device having a substantially undoped channel region includes performing an ion implantation into a substrate, depositing a first epitaxial layer over the substrate, and depositing a second epitaxial layer over the first epitaxial layer. In various examples, a plurality of fins is formed extending from the substrate. Each of the plurality of fins includes a portion of the ion implanted substrate, a portion of the first epitaxial layer, and a portion of the second epitaxial layer. In some embodiments, the portion of the second epitaxial layer of each of the plurality of fins includes an undoped channel region. In various embodiments, the portion of the first epitaxial layer of each of the plurality of fins is oxidized.

First claim

What is claimed is:

1. A method of semiconductor device fabrication, comprising:
performing an ion implantation into a substrate, thereby providing an ion implanted substrate;
after performing the ion implantation, depositing a first epitaxial layer over the substrate and a second epitaxial layer over the first epitaxial layer;
forming a plurality of fins extending from the substrate and including a trench disposed between the plurality of fins, wherein each of the plurality of fins includes a portion of the ion implanted substrate, a portion of the first epitaxial layer, and a portion of the second epitaxial layer, and wherein the portion of the second epitaxial layer of each of the plurality of fins includes an undoped channel region; and
prior to filling the trench disposed between the plurality of fins, oxidizing both the portion of the first epitaxial layer and sidewalls of the portion of the second epitaxial layer of each of the plurality of fins, and removing the oxidized sidewalls of the portion of the second epitaxial layer.

2. The method of claim 1 , wherein the undoped channel region has a dopant concentration of less than about 1×10 17 cm −3 .

3. The method of claim 1 , wherein the portion of the ion implanted substrate of each of the plurality of fins has a dopant concentration of between about 1×10 18 cm −3 and 1×10 19 cm −3 .

4. The method of claim 1 , wherein the substrate includes at least one zero-layer alignment mark, and wherein performing the ion implantation into the substrate includes aligning the ion implantation by way of the at least one zero-layer alignment mark.

5. The method of claim 4 , wherein the at least one zero-layer alignment mark includes a plurality of dielectric-filled trenches, wherein the second epitaxial layer includes silicon (Si), and wherein the depositing the second epitaxial layer forms polycrystalline Si over the plurality of dielectric-filled trenches.

6. The method of claim 1 , wherein the first epitaxial layer has a first oxidation rate, and wherein the second epitaxial layer has a second oxidation rate less than the first oxidation rate.

7. The method of claim 1 , wherein the oxidizing the sidewalls of the portion of the second epitaxial layer changes a profile of the sidewalls of the portion of the second epitaxial layer of each of the plurality of fins.

8. The method of claim 1 , wherein the first epitaxial layer includes silicon germanium (SiGe) and the second epitaxial layer includes silicon (Si).

9. The method of claim 8 ,
wherein the oxidizing the portion of the first epitaxial layer forms non-bonding Ge residue within the oxidized portion of the first epitaxial layer; and
wherein an anneal process is performed to eliminate the non-bonding Ge residue from within the oxidized portion of the first epitaxial layer.

10. A method, comprising:
providing a substrate including a first region and a second region, wherein the first region includes a zero-layer alignment mark;
using the zero-layer alignment mark to pattern a substrate implant region;
performing an ion implantation into the patterned substrate implant region, thereby forming an ion-implanted substrate region;
after performing the ion implantation, depositing a first epitaxial layer over the substrate and a second epitaxial layer over the first epitaxial layer;
forming, in the second region, a plurality of fins extending from the substrate, wherein each of the plurality of fins includes a portion of the ion-implanted substrate region, a first epitaxial layer region over the portion of the ion-implanted substrate region, and an undoped second epitaxial layer region over the first epitaxial layer region; and
oxidizing both the first epitaxial layer portion and sidewalls of the undoped second epitaxial layer region of each of the plurality of fins, and removing the oxidized sidewalls of the undoped second epitaxial layer region.

11. The method of claim 10 , wherein the undoped second epitaxial layer region includes a channel region, and wherein the undoped second epitaxial layer region has a dopant concentration of less than about 1×10 17 cm −3 .

12. The method of claim 10 , wherein the depositing the first and second epitaxial layers includes depositing the first and second epitaxial layers over the first and second regions, wherein the second epitaxial layer deposited over the first region includes a polycrystalline material, and wherein the second epitaxial layer deposited over the second region includes a crystalline material.

13. The method of claim 12 , wherein the zero-layer alignment mark includes a plurality of dielectric-filled trenches, wherein the second epitaxial layer includes silicon (Si), and wherein the depositing the second epitaxial layer forms polycrystalline Si over the dielectric-filled trenches.

14. The method of claim 10 , wherein the first epitaxial layer has a first oxidation rate, and wherein the second epitaxial layer has a second oxidation rate less than the first oxidation rate.

15. A method, comprising:
providing a substrate including an alignment region and a device region, wherein the alignment region and the device region are two different regions of the substrate;
forming a plurality of fin elements in the device region, wherein each of the plurality of fin elements includes a doped layer, a dielectric layer over the doped layer, and an undoped layer over the dielectric layer, wherein the undoped layer includes oxidized sidewalls that are formed as a result of forming the dielectric layer; and
after removing the oxidized sidewalls from the undoped layer, forming a gate stack over the undoped layer;
wherein the doped layer includes an anti-punch through doped region; and
wherein the undoped layer includes a channel region.

16. The method of claim 15 , wherein the dielectric layer has a thickness of between about 2-10 nm.

17. The method of claim 15 , wherein the doped layer includes doped Si, the dielectric layer includes oxidized SiGe, and the undoped layer includes undoped crystalline Si.

18. The method of claim 15 , further comprising:
forming a zero-layer alignment mark in the alignment region, wherein the zero-layer alignment mark includes a plurality of dielectric-filled trenches; and
depositing a polycrystalline layer over the plurality of dielectric-filled trenches.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Wang Chih-Hao
• Tsai Ching-Wei
• Ching Kuo-Cheng
• Liaw Jhon Jhy
• Lien Wai-Yi

Classifications

• H10P14/6308

  of Group IV semiconductors · CPC title

• H10P14/3411

  Silicon, silicon germanium or germanium · CPC title

• H10W46/501

  for use before dicing · CPC title

• H10W46/301

  for alignment · CPC title

• H10W46/101

  characterised by the type of information, e.g. logos or symbols · CPC title