Field effect transistors having ferroelectric or antiferroelectric gate dielectric structure

Patent metadata

Field	Value
Publication number	US-11735652-B2
Application number	US-201716635739-A
Country	US
Kind code	B2
Filing date	Sep 28, 2017
Priority date	Sep 28, 2017
Publication date	Aug 22, 2023
Grant date	Aug 22, 2023

Abstract

Field effect transistors having a ferroelectric or antiferroelectric gate dielectric structure are described. In an example, an integrated circuit structure includes a semiconductor channel structure includes a monocrystalline material. A gate dielectric is over the semiconductor channel structure. The gate dielectric includes a ferroelectric or antiferroelectric polycrystalline material layer. A gate electrode has a conductive layer on the ferroelectric or antiferroelectric polycrystalline material layer, the conductive layer including a metal. A first source or drain structure is at a first side of the gate electrode. A second source or drain structure is at a second side of the gate electrode opposite the first side.

First claim

What is claimed is:

1. An integrated circuit structure, comprising:
a semiconductor channel structure comprising a monocrystalline material;
a gate dielectric over the semiconductor channel structure, the gate dielectric comprising a ferroelectric or antiferroelectric polycrystalline material layer, the ferroelectric or antiferroelectric polycrystalline material layer having an uppermost surface, and the gate dielectric further comprising an amorphous oxide layer between the ferroelectric or antiferroelectric polycrystalline material layer and the semiconductor channel structure, wherein the ferroelectric or antiferroelectric polycrystalline material layer is on and in direct contact with the amorphous oxide layer, and wherein the amorphous oxide layer is on and in direct contact with the semiconductor channel structure;
a gate electrode having a conductive layer on and in direct contact with the ferroelectric or antiferroelectric polycrystalline material layer, the conductive layer comprising a metal, and the conductive layer having an uppermost surface co-planar with the uppermost surface of the ferroelectric or antiferroelectric polycrystalline material layer, and the gate electrode having a gate fill layer on and in direct contact with the conductive layer;
a first source or drain structure at a first side of the gate electrode; and
a second source or drain structure at a second side of the gate electrode opposite the first side.

2. The integrated circuit structure of claim 1 , wherein the ferroelectric or antiferroelectric polycrystalline material layer is a ferroelectric polycrystalline material layer.

3. The integrated circuit structure of claim 2 , wherein the ferroelectric polycrystalline material layer is an oxide comprising Zr and Hf with a Zr:Hf ratio of 50:50 or greater in Zr.

4. The integrated circuit structure of claim 2 , wherein the ferroelectric polycrystalline material layer has at least 80% orthorhombic crystallinity.

5. The integrated circuit structure of claim 1 , wherein the ferroelectric or antiferroelectric polycrystalline material layer is an antiferroelectric polycrystalline material layer.

6. The integrated circuit structure of claim 5 , wherein the antiferroelectric polycrystalline material layer is an oxide comprising Zr and Hf with a Zr:Hf ratio of 80:20 or greater in Zr.

7. The integrated circuit structure of claim 5 , wherein the antiferroelectric polycrystalline material layer has at least 80% tetragonal crystallinity.

8. An integrated circuit structure, comprising:
a semiconductor channel structure comprising a monocrystalline material;
a gate dielectric over the semiconductor channel structure, the gate dielectric comprising a ferroelectric or antiferroelectric polycrystalline material layer, the ferroelectric or antiferroelectric polycrystalline material layer having an uppermost surface, and the gate dielectric further comprising an amorphous oxide layer between the ferroelectric or antiferroelectric polycrystalline material layer and the semiconductor channel structure, wherein the ferroelectric or antiferroelectric polycrystalline material layer is on and in direct contact with the amorphous oxide layer, and wherein the amorphous oxide layer is on and in direct contact with the semiconductor channel structure;
a gate electrode having a conductive layer on and in direct contact with the ferroelectric or antiferroelectric polycrystalline material layer, the conductive layer comprising a metal, and the conductive layer having an uppermost surface co-planar with the uppermost surface of the ferroelectric or antiferroelectric polycrystalline material layer, and the gate electrode having a gate fill layer on and in direct contact with the conductive layer;
a first source or drain structure at a first side of the gate electrode;
a first dielectric spacer between the first source or drain structure and the first side of the gate electrode;
a second source or drain structure at a second side of the gate electrode opposite the first side; and
a second dielectric spacer between the second source or drain structure and the second side of the gate electrode.

9. The integrated circuit structure of claim 8 , wherein the ferroelectric or antiferroelectric polycrystalline material layer extends along the first dielectric spacer and the second dielectric spacer.

10. The integrated circuit structure of claim 8 , wherein the ferroelectric or antiferroelectric polycrystalline material layer is a ferroelectric polycrystalline material layer.

11. The integrated circuit structure of claim 10 , wherein the ferroelectric polycrystalline material layer is an oxide comprising Zr and Hf with a Zr:Hf ratio of 50:50 or greater in Zr.

12. The integrated circuit structure of claim 10 , wherein the ferroelectric polycrystalline material layer has at least 80% orthorhombic crystallinity.

13. The integrated circuit structure of claim 8 , wherein the ferroelectric or antiferroelectric polycrystalline material layer is an antiferroelectric polycrystalline material layer.

14. The integrated circuit structure of claim 13 , wherein the antiferroelectric polycrystalline material layer is an oxide comprising Zr and Hf with a Zr:Hf ratio of 80:20 or greater in Zr.

15. The integrated circuit structure of claim 13 , wherein the antiferroelectric polycrystalline material layer has at least 80% tetragonal crystallinity.

16. An integrated circuit structure, comprising:
a semiconductor channel structure comprising a monocrystalline material;
a gate dielectric over the semiconductor channel structure, the gate dielectric comprising an amorphous oxide layer;
a gate electrode above the gate dielectric, the gate electrode having a conductive layer having an uppermost surface, and the gate electrode having a gate fill layer on and in direct contact with the conductive layer;
a first source or drain structure at a first side of the gate electrode;
a first dielectric spacer between the first source or drain structure and the first side of the gate electrode;
a second source or drain structure at a second side of the gate electrode opposite the first side;
a second dielectric spacer between the second source or drain structure and the second side of the gate electrode; and
a ferroelectric or antiferroelectric polycrystalline material layer adjacent the first and second dielectric spacers and adjacent the gate dielectric, the ferroelectric or antiferroelectric polycrystalline material layer having an uppermost surface co-planar with the uppermost surface of the gate electrode, wherein the ferroelectric or antiferroelectric polycrystalline material layer is on and in direct contact with the amorphous oxide layer of the gate dielectric, wherein the conductive layer of the gate electrode is on and in direct contact with the ferroelectric or antiferroelectric polycrystalline material layer, and wherein the amorphous oxide layer is on and in direct contact with the semiconductor channel structure.

17. The integrated circuit structure of claim 16 , wherein the ferroelectric or antiferroelectric polycrystalline material layer is an oxide comprising Zr and Hf, and wherein the gate dielectric comprises a layer of amorphous hafnium oxide.

18. The integrated circuit structure of claim 17 , wherein the ferroelectric or antiferroelectric polycrystalline material layer has at least 80% orthorhombic crystallinity.

19. The integrated circuit structure of claim 17 , wherein the ferroelectric or antiferroelectric polycrystalline material layer has at least 80%

Assignees

• Intel Corp

Inventors

• Kim Seiyon
• Avci Uygar E
• Howard Joshua M
• Young Ian A
• Morris Daniel H

Classifications

• H10D30/0415 Primary

  of FETs having ferroelectric gate insulators · CPC title

• H10D64/689

  having ferroelectric layers · CPC title

• H10D30/60 Primary

  Insulated-gate field-effect transistors [IGFET] (H10D30/40 takes precedence) · CPC title

• H01L29/6684 Primary

  Electricity · mapped topic

• H01L29/516

  Electricity · mapped topic