Method for forming a bioFET sensor including semiconductor fin or nanowire

Patent metadata

Field	Value
Publication number	US-11735645-B2
Application number	US-202017099339-A
Country	US
Kind code	B2
Filing date	Nov 16, 2020
Priority date	Nov 21, 2019
Publication date	Aug 22, 2023
Grant date	Aug 22, 2023

Abstract

A method for forming a sensor is provided. The method includes: providing an active region comprising a channel having: a length, and a periphery consisting of one or more surfaces having said length, said periphery comprising a first part and a second part, each part having said length, the first part representing from 10 to 75% of the area of the periphery and the second part representing from 25 to 90% of the area of the periphery; providing a first dielectric structure on the entire first part, the first dielectric structure having a maximal equivalent oxide thickness; and providing a second dielectric structure on the entire second part, the second dielectric structure having a minimal equivalent oxide thickness larger than the maximal equivalent oxide thickness of the first dielectric structure.

First claim

What is claimed:

1. A method for forming a sensor, the method comprising:
providing an active region comprising a source region, a drain region, and a semiconductor channel region between the source region and the drain region, the semiconductor channel region having:
a length, and
a periphery consisting of one or more surfaces having said length, said periphery comprising a first part and a second part, the second part being different from the first part, each part having said length, the first part representing from 10 to 75% of an area of the periphery and the second part representing from 25 to 90% of the area of the periphery;

providing a first dielectric structure on the first part of the periphery, the first dielectric structure having a maximal equivalent oxide thickness, measured perpendicularly to the first part, thereby forming a gate dielectric suitable for being exposed to a fluid to be sensed; and
providing a second dielectric structure on the second part of the periphery, the second dielectric structure having a minimal equivalent oxide thickness, measured perpendicularly to the second part of the periphery, that is larger than the maximal equivalent oxide thickness of the first dielectric structure, thereby forming an isolation structure.

2. The method according to claim 1 , further comprising:
providing a cavity having an interior, wherein the cavity is suitable for containing the fluid, and wherein the gate dielectric is exposed to said interior; and
providing a reference electrode, spatially separated from the gate dielectric, and exposed to said interior.

3. The method according to claim 1 , wherein the first part of the periphery represents from 10 to 45% of the area of the periphery, and wherein the second part of the periphery represents from 55 to 90% of the area of the periphery.

4. The method according to claim 1 , wherein the active region is comprised in a fin or a nanowire.

5. The method according to claim 1 , wherein the periphery comprises a top surface, a bottom surface, and sidewall surfaces, wherein the first part of the periphery is the top surface and wherein the second part of the periphery comprise the sidewall surfaces.

6. The method according to claim 5 , wherein the second part of the periphery consists of the sidewall surfaces.

7. The method according to claim 5 , wherein the second part of the periphery consists of the sidewall surfaces and the bottom surface.

8. The method according to claim 5 , wherein the sidewall surfaces have a width, wherein the second dielectric structure covers the width (Ws), and wherein a part of the second dielectric structure extends farther than the width (Ws) so as to form a cavity delimited by a top surface of the first dielectric structure and the part of the second dielectric structure extending farther than the width (Ws).

9. The method according to claim 8 , wherein the second part of the periphery consists of the sidewall surfaces.

10. The method according to claim 8 , wherein the second part of the periphery consists of the sidewall surfaces and the bottom surface.

11. The method according to claim 1 , wherein the periphery comprises a top surface, a bottom surface and sidewall surfaces, wherein the first part of the periphery is the sidewall surfaces and wherein the second part of the periphery is the top surface and the bottom surface.

12. The method according to claim 11 , wherein the top surface has a width (Wu) and wherein the second dielectric structure is present over the width (Wu) of the top surface and extends farther than the width (Wu).

13. The method according to claim 4 , wherein the active region is comprised in a nanowire, wherein the periphery comprises a top surface, a bottom surface, and sidewall surfaces, and wherein the first part is the bottom surface and the second part is the top surface and the sidewall surfaces.

14. The method according to claim 1 , wherein the maximal equivalent oxide thickness of the first dielectric structure ranges from 0.5 nm to 4 nm.

15. The method according to claim 1 , wherein the minimal equivalent oxide thickness of the second dielectric structure is larger than 10 nm.

16. The method according to claim 1 , wherein the semiconductor channel region has a width (Wc) and a height (Hc) which are both smaller than 10 nm.

17. The method according to claim 1 , wherein the semiconductor channel region has a width (Wc) and a height (Hc) which are both smaller than than 6 nm.

18. The method according to claim 1 , wherein the first part of the periphery comprises a semiconductor channel surface with Miller indices {001}.

19. The method according to claim 1 , wherein the first part of the periphery and the second part of the periphery add up to at least 60%, at least 70%, at least 80%, at least 90%, or at least 95% of the area of the periphery.

20. The method according to claim 19 , wherein the first part of the periphery and the second part of the periphery add up to 100% of the area of the periphery.

Assignees

• Imec Vzw
• Katholieke Univ Leuven Ku Leuven R & D
• Univ Leuven Kath

Inventors

• Martens Koen
• Santermans Sybren
• Hellings Geert
• Barge David

Classifications

• H10D64/021 Primary

  using multiple gate spacer layers, e.g. bilayered sidewall spacers · CPC title

• H10D30/60 Primary

  Insulated-gate field-effect transistors [IGFET] (H10D30/40 takes precedence) · CPC title

• H01L29/6656 Primary

  Electricity · mapped topic

• G01N27/4145

  specially adapted for biomolecules, e.g. gate electrode with immobilised receptors · CPC title

• G01N27/414

  Ion-sensitive or chemical field-effect transistors, i.e. ISFETS or CHEMFETS · CPC title