Nanofluid sensor with real-time spatial sensing

Patent metadata

Field	Value
Publication number	US-9733210-B2
Application number	US-201414587941-A
Country	US
Kind code	B2
Filing date	Dec 31, 2014
Priority date	Dec 31, 2014
Publication date	Aug 15, 2017
Grant date	Aug 15, 2017

Abstract

A semiconductor structure capable of real-time spatial sensing of nanoparticles within a nanofluid is provided. The structure includes an array of gate structures. An interlevel dielectric material surrounds the array of gate structures. A vertical inlet channel is located within a portion of the interlevel dielectric material and on one side of the array of gate structures. A vertical outlet channel is located within another portion of the interlevel dielectric material and on another side of the array of gate structures. A horizontal channel that functions as a back gate is in fluid communication with the vertical inlet and outlet channels, and is located beneath the array of gate structures. A back gate dielectric material portion lines exposed surfaces within the vertical inlet channel, the vertical outlet channel and the horizontal channel.

First claim

What is claimed as new is:

1. A semiconductor structure comprising:
a nanofluid sensor for sensing nanoparticles in a nanofluid, said nanofluid sensor comprising:
an array of gate structures, each gate structure of the array of gate structures is located on a semiconductor material portion;
an interlevel dielectric material surrounding said array of gate structures;
a vertical inlet channel located within a portion of said interlevel dielectric material and located on one side of said array of gate structures;
a vertical outlet channel located within another portion of said interlevel dielectric material and located on another side of said array of gate structures;
a horizontal channel connected to said vertical inlet and outlet channels, located beneath said array of gate structures, and vertically separating said array of gate structures from an underlying handle substrate; and
a back gate dielectric material portion lining the entirety of exposed surfaces within each of said vertical inlet channel, said vertical outlet channel and said horizontal channel, and said back gate dielectric material portion extends to at least a topmost surface of said interlevel dielectric material.

2. The semiconductor structure of claim 1 , wherein said array of gate structures are sacrificial gate structures.

3. The semiconductor structure of claim 2 , wherein each sacrificial gate structure comprises, from bottom to top, a front gate dielectric material portion and a front sacrificial gate material portion.

4. The semiconductor structure of claim 2 , further comprising a dielectric spacer located on sidewall surfaces of each sacrificial gate structure.

5. The semiconductor structure of claim 2 , further comprising a trench isolation structure separating each sacrificial gate structure of said array of gate structures.

6. The semiconductor structure of claim 2 , further comprising a source region located within each semiconductor material portion and on one side of each sacrificial gate structure, and a drain region located within each semiconductor material portion and on another side of each sacrificial gate structure.

7. The semiconductor structure of claim 2 , further comprising a logic gate structure located laterally adjacent said array of gate structures, said logic gate structure is present on another semiconductor material portion, and wherein an insulator layer portion is located directly beneath said another semiconductor material portion.

8. The semiconductor structure of claim 1 , wherein said array of gate structures are functional gate structures comprising a front gate dielectric material portion and a front gate material portion.

9. The semiconductor structure of claim 8 , further comprising a dielectric spacer located on sidewall surfaces of each gate structure.

10. The semiconductor structure of claim 8 , further comprising a trench isolation structure separating each functional structure of said array of gate structures.

11. The semiconductor structure of claim 8 , further comprising a source region located within each semiconductor material portion and on one side of each functional gate structure, and a drain region located within each semiconductor material portion and on another side of each functional gate structure.

12. The semiconductor structure of claim 8 , further comprising a logic gate structure located laterally adjacent said array of gate structures, said logic gate structure is present on another semiconductor material portion, and wherein an insulator layer portion is located directly beneath said another semiconductor material portion.

13. The semiconductor structure of claim 1 , wherein said back gate dielectric material portion has a topmost surface that is coplanar with said topmost surface of said interlevel dielectric material.

14. The semiconductor structure of claim 1 , wherein said back gate dielectric material portion is present on said topmost surface of said interlevel dielectric material.

Assignees

• IBM

Inventors

• Cheng Kangguo
• Khakifirooz Ali
• Shahidi Ghavam G
• Shahrjerdi Davood

Classifications

• G01N27/4145 Primary

  specially adapted for biomolecules, e.g. gate electrode with immobilised receptors · CPC title

• G01N27/4146

  involving nanosized elements, e.g. nanotubes, nanowires · CPC title

• G01N27/4148

  Integrated circuits therefor, e.g. fabricated by CMOS processing · CPC title

• H01L21/84

  Electricity · mapped topic

• H01L27/1203

  Electricity · mapped topic