Structure and method to self align via to top and bottom of tight pitch metal interconnect layers
US-2017263553-A1 · Sep 14, 2017 · US
US11735524B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-11735524-B2 |
| Application number | US-201916576201-A |
| Country | US |
| Kind code | B2 |
| Filing date | Sep 19, 2019 |
| Priority date | Mar 22, 2016 |
| Publication date | Aug 22, 2023 |
| Grant date | Aug 22, 2023 |
A practical reading order for non-experts. Skip the full description unless you need deep technical detail.
What the patent document calls the invention.
A short plain-language summary of the technical disclosure.
Who owns or filed the patent and who is credited as inventor.
Filing, priority, publication, and grant dates set the timeline.
The legal scope of protection — read this for what is actually claimed.
Technology tags used to group this patent with similar filings.
Prior art links and similar publications in this corpus.
Official abstract text for this publication.
An electrical device includes a plurality of metal lines in a region of a substrate positioned in an array of metal lines all having parallel lengths, and a plurality of air gaps between the metal lines in a same level as the metal lines, wherein an air gap is present between each set of adjacent metal lines. A plurality of interconnects may be present in electrical communication with said plurality of metal lines, wherein an exclusion zone for said plurality of interconnects is not present in said array of metal lines.
Opening claim text (preview).
What is claimed is: 1. An electrical device comprising: a plurality of electrically conductive lines on a substrate that are positioned in an array having parallel lengths; a plurality of air gaps between the plurality of electrically conductive lines and in a same level as the plurality of electrically conductive lines, wherein one air gap of the plurality of air gaps is present between each adjacent pair of the plurality of electrically conductive lines; and a plurality of interconnects in electrical communication with said plurality of electrically conductive lines, wherein an exclusion zone for said plurality of interconnects is not present in said array of electrically conductive lines. 2. The electrical device of claim 1 , wherein the plurality of interconnects do not enter the air gaps. 3. The electrical device of claim 1 , wherein a pitch separating adjacent ones of the plurality of electrically conductive lines in the plurality of electrically conductive lines ranges from 30 nm to 80 nm. 4. The electrical device of claim 1 , wherein each of the plurality of electrically conductive lines is comprised of a doped semiconductor material. 5. The electrical device of claim 1 , wherein each of the plurality of electrical conductive lines is comprised of a metal. 6. The electrically device of claim 5 , wherein the metal of the plurality of electrically conductive lines is present in trenches in a low-k dielectric material. 7. An electrical device comprising: a plurality of electrically conductive lines on a substrate that are positioned in an array having parallel lengths; a plurality of air gaps between the plurality of electrically conductive lines and in a same level as the plurality of electrically conductive lines, wherein one air gap of the plurality of air gaps is present between each adjacent pair of the plurality of electrically conductive lines; and a plurality of interconnects in electrical communication and self-aligned with said plurality of electrically conductive lines, wherein an exclusion zone for said plurality of interconnects is not present in said array of electrically conductive lines. 8. The electrical device of claim 7 , wherein the plurality of interconnects do not enter the air gaps. 9. The electrical device of claim 7 , wherein a pitch separating adjacent ones of the plurality of electrically conductive lines in the plurality of electrically conductive lines ranges from 30 nm to 80 nm. 10. The electrical device of claim 7 , wherein each of the plurality of electrically conductive lines is comprised of a doped semiconductor material. 11. The electrical device of claim 7 , wherein each of the plurality of electrically conductive lines are comprised of a metal present in trenches in a low-k dielectric material.
by forming self-aligned vias · CPC title
by chemical means · CPC title
by chemical means · CPC title
using decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition (deposition by physical ablation of a target H10P14/6329) · CPC title
using physical ablation of a target, e.g. physical vapour deposition or pulsed laser deposition · CPC title
Related publications grouped by family.
Answers are generated from the same data shown on this page.