Semiconductor devices including a capping layer

Patent metadata

Field	Value
Publication number	US-2016293547-A1
Application number	US-201615155539-A
Country	US
Kind code	A1
Filing date	May 16, 2016
Priority date	Aug 1, 2013
Publication date	Oct 6, 2016
Grant date	—

Abstract

Methods of forming a semiconductor device are provided. A method of forming a semiconductor device may include forming a capping layer on a metal pattern and on an adjacent portion of an insulating layer, the capping layer comprising a first etch selectivity, with respect to the insulating layer, on the metal pattern and a second etch selectivity, with respect to the insulating layer, on the portion of the insulating layer. Moreover, the method may include forming a recess region adjacent the metal pattern by removing the capping layer from the portion of the insulating layer. At least a portion of the capping layer may remain on an uppermost surface of the metal pattern after removing the capping layer from the portion of the insulating layer. Related semiconductor devices are also provided.

First claim

What is claimed is:

1 . A semiconductor device comprising:
a plurality of lower metal lines spaced apart by a first distance to provide respective lower spaces between directly adjacent ones of the lower metal lines on a lower dielectric layer; a plurality of lower voids, respective ones of which are located in the respective lower spaces, wherein each of the lower voids has a first maximum width; a plurality of upper metal lines spaced apart by a second distance to provide respective upper spaces between directly adjacent ones of the upper metal lines on the plurality of lower metal lines; and a plurality of upper voids, respective ones of which are located in the respective upper spaces, wherein each of the upper voids has a second maximum width that is different from the first maximum width.

2 . The device of claim 1 wherein the second maximum width is greater than the first maximum width.

3 . The device of claim 1 wherein the first maximum width is located closest to the lower dielectric layer and the second maximum width is located closest to the plurality of lower metal lines.

4 . The device of claim 1 wherein the first distance is less than the second distance.

5 . The device of claim 4 wherein the first distance is located closest to the lower dielectric layer and the second distance is located closest to the plurality of lower metal lines.

6 . The device of claim 1 wherein the upper metal lines and the lower metal lines have different widths.

7 . The device of claim 6 wherein a minimum width of the upper metal lines is greater than a minimum width of the lower metal lines.

8 . The device of claim 7 wherein the minimum width of the lower metal lines is located closest to the lower dielectric layer and the minimum width of the upper metal lines is located closest to the plurality of lower metal lines.

9 . The device of claim 1 wherein the first and second distances are different.

10 . The device of claim 1 wherein the upper and lower voids comprise low-K dielectric voids.

11 . The device of claim 1 wherein structures are in a first region of the device, the device further comprising:
metal lines in a second region of the device and the lower layer dielectric filling spaces between the metal lines in the second region.

12 . The device of claim 1 wherein the plurality of lower metal lines comprise a plurality of first lower metal lines in a first region of the device, the device further comprising:
an enlarged lower void included in the plurality of lower voids having a maximum width that is greater than the first maximum width;
a second region of the device laterally spaced apart from the first region of the device; and
a plurality of second lower metal lines on the lower dielectric layer in the second region, wherein respective second lower spaces between directly adjacent ones of the plurality of the second lower metal lines are free of voids.

13 . The device of claim 12 wherein the enlarged lower void is directly adjacent to an edge of the second region of the device.

14 . The device of claim 13 wherein the edge comprises a sidewall of the lower dielectric layer in the second region.

15 . The device of claim 1 wherein respective centers of a first one of the plurality of lower metal lines and a first one of the plurality of upper metal lines are aligned to one another.

16 . The device of claim 15 wherein respective centers of a second one of the plurality of lower metal lines and a second one of the plurality of upper metal lines are misaligned with one another.

17 . The device of claim 1 , further comprising a buffer insulating layer conformally covering the lower metal lines.

18 . The device of claim 17 , further comprising capping patterns on the lower metal lines, respectively,
wherein the capping layer comprises a metal nitride, and wherein the buffer insulating layer covers top surfaces of the capping patterns.

19 . The device of claim 17 , wherein the buffer insulating layer comprises SiN, SiON, SiC, SiCN, SiOCH, SiOC, or SiOF.

20 . A semiconductor device comprising:
first and second regions on a lower dielectric layer of the device; a plurality of lower metal lines spaced apart in the first and second regions of the device by a first distance to provide respective lower spaces between directly adjacent ones of the lower metal lines on the lower dielectric layer; a plurality of lower voids, respective ones of which are located in the respective lower spaces, wherein each of the lower voids has a first maximum width; a plurality of first upper metal lines spaced apart in the first region by the first distance to provide respective first upper spaces between directly adjacent ones of the first upper metal lines on the lower metal lines in the first region; a plurality of first upper voids, respective ones of which are located in the respective first upper spaces, wherein each of the first upper voids has the first maximum width, wherein respective centers of the lower voids in the first region and the first upper voids in the first region are aligned to one another; a plurality of second upper metal lines spaced apart in the second region by the first distance to provide respective second upper spaces between directly adjacent ones of the second upper metal lines on the lower metal lines in the second region; and a plurality of second upper voids, respective ones of which are located in the respective second upper spaces, wherein each of the second upper voids has the first maximum width, wherein respective centers of the lower voids in the second region and the second upper voids in the second region are misaligned with one another.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Rha Sangho
• Baek Jongmin
• You Wookyung
• Ahn Sanghoon
• Lee Nae-In

Classifications

• H10P52/403

  of conductive or resistive materials · CPC title

• H10P50/00

  Etching of wafers, substrates or parts of devices · CPC title

• H10P14/69391

  the material containing aluminium, e.g. Al2O3 · CPC title

• H10P14/6339

  deposition by cyclic CVD, e.g. ALD, ALE or pulsed CVD · CPC title

• H10P14/6336

  in the presence of a plasma [PECVD] · CPC title