Methods of forming wiring structures

Patent metadata

Field	Value
Publication number	US-9281277-B2
Application number	US-201414527842-A
Country	US
Kind code	B2
Filing date	Oct 30, 2014
Priority date	Dec 23, 2013
Publication date	Mar 8, 2016
Grant date	Mar 8, 2016

Abstract

A wiring structure includes a first insulation layer, a plurality of wiring patterns, a protection layer pattern and a second insulation layer. The first insulation layer may be formed on a substrate. A plurality of wiring patterns may be formed on the first insulation layer, and each of the wiring patterns may include a metal layer pattern and a barrier layer pattern covering a sidewall and a bottom surface of the metal layer pattern. The protection layer pattern may cover a top surface of each of the wiring patterns and including a material having a high reactivity with respect to oxygen. The protection layer pattern may cover a top surface of each of the wiring patterns and including a material having a high reactivity with respect to oxygen.

First claim

What is claimed is:

1. A method of forming a wiring structure, the method comprising:
forming, on a substrate, a first insulation layer that includes a plurality of trenches therein;
forming a barrier layer in the plurality of trenches and on an upper surface of the first insulation layer;
forming a metal layer on the barrier layer to fill the plurality of trenches;
planarizing upper portions of the metal layer and the barrier layer until the upper surface of the first insulation layer is exposed to form a metal layer pattern having a first oxide layer thereon and a barrier layer pattern having a second oxide layer thereon;
performing an ultraviolet (UV) pre-treatment process using UV and a reducing gas on the metal layer pattern and the barrier layer pattern to remove the first and second oxide layers thereon, respectively, so as to form a plurality of wiring patterns, wherein the plurality of wiring patterns include the barrier layer pattern and the metal layer pattern;
forming a protection layer pattern directly on top surfaces of the plurality of wiring patterns, the protection layer pattern including a material having a high reactivity with respect to oxygen;
partially removing the first insulation layer to form recesses between the plurality of wiring patterns; and
forming a second insulation layer on the protection layer pattern and the first insulation layer to form an air gap between the plurality of wiring patterns.

2. The method of claim 1 , wherein the UV pre-treatment process and forming the protection layer pattern are performed in a vacuum chamber.

3. The method of claim 1 , wherein the reducing gas includes hydrogen gas and/or ammonia gas.

4. The method of claim 1 , wherein the UV pre-treatment process is performed at a temperature of about 250° C. to about 400° C.

5. The method of claim 1 , wherein the barrier layer includes Ta, TaN, TaC, TaCN, Ti, TiN and/or WN.

6. The method of claim 1 , wherein the metal layer includes copper.

7. The method of claim 1 , after performing the UV pre-treatment process, the method further comprising performing a plasma treatment process using ammonia gas.

8. The method of claim 7 , wherein the UV pre-treatment process and the plasma treatment process are performed in vacuum chambers that are different from each other.

9. The method of claim 1 , wherein the protection layer pattern includes aluminum nitride and/or cobalt.

10. The method of claim 1 , wherein forming the protection layer pattern comprises:
forming the protection layer pattern using a metal nitride on the top surface of each of the plurality of wiring patterns; and
forming a sacrificial layer pattern including a metal oxynitride on the first insulation layer.

11. The method of claim 10 , wherein forming the protection layer pattern comprises performing a chemical vapor deposition (CVD) process using an aluminum nitride precursor to form the sacrificial layer pattern including aluminum oxynitride and the protection layer pattern including aluminum nitride.

12. The method of claim 10 , wherein the sacrificial layer pattern is etched prior to partially removing the first insulation layer.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Baek Jong-Min
• Rha Sang-Ho
• You Woo-Kyung
• Ahn Sang-Hoon
• Lee Nae-In
• Kim Ki-Chul
• Lee Jeon-Il

Classifications

• H10W20/0765

  the thin functional dielectric layers being temporary, e.g. sacrificial layers · CPC title

• H10W20/495

  Capacitive arrangements or effects of, or between wiring layers · CPC title

• H10W20/077

  on sidewalls or on top surfaces of conductors (H10W20/076 takes precedence) · CPC title

• H10W20/072

  of dielectric parts comprising air gaps · CPC title

• H10W20/062

  by smoothing of conductive parts, e.g. by planarisation · CPC title