Trench structures for three-dimensional memory devices

Patent metadata

Field	Value
Publication number	US-11729971-B2
Application number	US-202117645102-A
Country	US
Kind code	B2
Filing date	Dec 20, 2021
Priority date	Mar 7, 2017
Publication date	Aug 15, 2023
Grant date	Aug 15, 2023

Abstract

The present disclosure describes method and structure of a three-dimensional memory device. The memory device includes a substrate and a plurality of wordlines extending along a first direction over the substrate. The first direction is along the x direction. The plurality of wordlines form a staircase structure in a first region. A plurality of channels are formed in a second region and through the plurality of wordlines. The second region abuts the first region at a region boundary. The memory device also includes an insulating slit formed in the first and second regions and along the first direction. A first width of the insulating slit in the first region measured in a second direction is greater than a second width of the insulating slit in the second region measured in the second direction.

First claim

What is claimed is:

1. A memory device, comprising:
a plurality of wordlines extending along a first lateral direction, wherein the plurality of wordlines form a staircase structure in a first region;
one or more rows of contact structures formed in the first region, wherein each row of the one or more rows of contact structures is positioned along the first lateral direction and comprises two or more contact structures;
a plurality of channels formed in a second region abutting the first region; and
a slit structure formed in the first and second regions, wherein:
the slit structure extends along the first lateral direction;
the slit structure comprises a first width in the first region and measured in a second lateral direction; and
the slit structure comprises a second width in the second region measured in the second lateral direction and is less than the first width, wherein a row of contact structures of the one or more rows of contact structures comprises first and second contact structures, and wherein the first contact structure and the slit structure are separated by a first lateral distance and the second contact structure and the slit structure are separated by a second lateral distance that is different from the first lateral distance.

2. The memory device of claim 1 , wherein the slit structure comprises an insulating material.

3. The memory device of claim 1 , wherein the slit structure in the first region comprises a rectangular shape.

4. The memory device of claim 1 , wherein the slit structure in the second region comprises a rectangular shape.

5. The memory device of claim 1 , wherein the second lateral direction is perpendicular to the first lateral direction.

6. The memory device of claim 1 , wherein each contact structure of the one or more rows of contact structures is electrically coupled to a wordline of the plurality of wordlines.

7. The memory device of claim 1 , wherein the first lateral distance is less than the second lateral distance.

8. The memory device of claim 1 , wherein the first contact structure is positioned further away from the second region than the second contact structure.

9. The memory device of claim 1 , wherein the first and second lateral directions are parallel to a top surface of a substrate.

10. The memory device of claim 1 , wherein the second width is substantially uniform along the first lateral direction.

11. A memory device, comprising:
a wordline staircase region;
one or more rows of contact structures formed in the wordline staircase region, wherein a row of contact structures of the one or more rows of contact structures are positioned along a first lateral direction and comprises first and second contact structures;
an array region abutting the wordline staircase region; and
a slit structure formed in the wordline staircase region and the array region, comprising:
a first portion formed in the wordline staircase region, wherein the first portion is separated from the first contact structure by a first lateral distance and separated from the second contact structure by a second lateral distance different from the first lateral distance, and wherein the first and second lateral distances are oriented along a second lateral direction perpendicular to the first lateral direction; and
a second portion formed in the array region.

12. The memory device of claim 11 , further comprising one or more rows of channels in the array region, wherein a given one of the one or more rows of channels extends along the first lateral direction and comprises first and second channels.

13. The memory device of claim 12 , wherein the second portion is separated from the first channel by a third lateral distance and separated from the second channel by a fourth lateral distance, wherein the third and fourth lateral distances are oriented in the second lateral direction and are substantially the same.

14. The memory device of claim 11 , wherein the slit structure continuously passes through the wordline staircase region and the array region.

15. The memory device of claim 11 , wherein a slit structure of the plurality of slit structures comprises a rectangular shape.

16. A memory device, comprising:
a wordline staircase region;
an array region abutting the wordline staircase region;
first and second slit structures extending along a first lateral direction, wherein each of the first and second slit structures continuously passes from a portion of the wordline staircase region to a portion of the array region, and wherein:
a first portion of the first slit structure and a first portion of the second slit structure are formed in the wordline staircase region; and
a second portion of the first slit structure and a second portion of the second slit structure are formed in the array region; and

a row of contact structures positioned along the first lateral direction and between the first portions of the first and second slit structures, wherein a first lateral distance between a first contact structure of the row of contact structures and the first portion of the first slit structure is greater than a second lateral distance between a second contact structure of the row of contact structures and the first portion of the first slit structure, and wherein the first and second lateral distances are oriented in a second lateral direction perpendicular to the first lateral direction.

17. The memory device of claim 16 , wherein a third lateral distance between the first contact structure and the first portion of the second slit structure is greater than the first lateral distance.

18. The memory device of claim 16 , further comprising a row of channels formed in the array region and between the second portions of the first and second slit structures.

19. The memory device of claim 18 , wherein a third lateral distance between a first channel of the row of channels and the second portion of the first slit structure is substantially the same as a fourth lateral distance between a second channel of the row of channels and the second portion of the first slit structure, and wherein the third and fourth lateral distances are oriented in the second lateral direction.

20. The memory device of claim 16 , wherein the first and second contact structures are positioned at different lateral distances away from the array region.

Assignees

• Yangtze Memory Tech Co Ltd

Inventors

• Xu Qiang
• Xia Zhiliang
• Yan Ping
• Li Guangji
• Huo Zongliang

Classifications

• H10W10/011

  of isolation regions comprising dielectric materials · CPC title

• H10W10/10

  Isolation regions comprising dielectric materials · CPC title

• H10D84/01

  Manufacture or treatment · CPC title

• H10D88/00 Primary

  Three-dimensional [3D] integrated devices · CPC title

• H10B43/20 Primary

  characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels · CPC title