Semiconductor device and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-10388605-B2
Application number	US-201815967086-A
Country	US
Kind code	B2
Filing date	Apr 30, 2018
Priority date	Jul 5, 2016
Publication date	Aug 20, 2019
Grant date	Aug 20, 2019

Abstract

A semiconductor device may include a first pattern. The semiconductor device may include a second pattern intersecting with the first pattern and including an intersection region with the first pattern and a non-intersection region.

First claim

What is claimed is:

1. A method of manufacturing a semiconductor device, comprising:
forming a stack;
forming a first slit insulating layer configured to pass through the stack and extend in a first direction, the first slit insulating layer including a first region, and a second region having a width greater than a width of the first region;
forming a slit configured to pass through the stack and the first slit insulating layer and extend in a second direction intersecting with the first direction, the slit intersecting with the first slit insulating layer in the first region; and
forming a second slit insulating layer in the slit.

2. The method according to claim 1 , wherein the first slit insulating layer has a tapered shape in which a width the first slit insulating layer is increased along the first direction.

3. The method according to claim 1 , wherein the first slit insulating layer has a first width on a first edge of the second slit insulating layer and has a second width on a second edge of the second slit insulating layer, and the first width has a value greater than the second width.

4. The method according to claim 3 , wherein a distance between the first edge and the end of the first slit insulating layer has a fourth width, and the fourth width has a value greater than ½ of the first width.

5. The method according to claim 4 , wherein an end of the first slit insulating layer that is adjacent to the first edge has a third width, and the third width has a value less than the first width and greater than the second width.

6. The method according to claim 1 , wherein an end of the first slit insulating layer that is adjacent to the first edge has a third width, and the third width is the same as the first width or has a value greater than the first width.

7. The method according to claim 1 , wherein the first slit insulating layer has a minimum width in the first region and is increased in width from the first region to both ends of the first slit insulating layer.

8. The method according to claim 1 , wherein the first slit insulating layer has a first width on a first edge of the second slit insulating layer, has a second width on a second edge of the second slit insulating layer, and has a third width between the first edge and the second edge, and the third width has a value less than the first width and the second width.

9. The method according to claim 8 , wherein an end of the first slit insulating layer has a fourth width, and the fourth width is the same as the first width or has a value greater than the first width.

10. The method according to claim 9 , wherein a distance between the first edge and the end of the first slit insulating layer has a fifth width, and the fifth width has a value greater than ½ of the first width.

11. The method according to claim 8 , wherein an end of the first slit insulating layer has a fourth width, and the fourth width has a value less than the first width and greater than the third width.

12. The method according to claim 1 , wherein the first slit insulating layer includes a seam disposed in the second region.

13. A method of manufacturing a semiconductor device, comprising:
forming a stack;
forming a first slit insulating layer configured to pass through the stack;
forming a slit configured to pass through the stack and the first slit insulating layer, the slit including a first region configured to intersect with the first slit insulating layer, and a second region configured not to intersect with the first slit insulating layer and having a width greater than a width of the first region; and
forming a second slit insulating layer in the slit, wherein the second slit insulating layer includes a seam disposed in the second region.

14. The method according to claim 13 , wherein the second slit insulating layer has a tapered shape in which a width of the second slit insulating layer is increased along a longitudinal direction of the second slit insulating layer.

15. The method according to claim 13 , wherein the second slit insulating layer has a first width on a first edge of the first slit insulating layer and has a second width on a second edge of the first slit insulating layer, and the first width has a value greater than the second width.

16. The method according to claim 15 , wherein an end of the second slit insulating layer that is adjacent to the first edge has a third width, and the third width is the same as the first width or has a value greater than the first width.

17. The method according to claim 15 , wherein a distance between the first edge and the end of the first slit insulating layer has a fourth width, and the fourth width has a value greater than ½ of the first width.

18. A method of manufacturing a semiconductor device, comprising:
forming a stack;
forming a first slit insulating layer configured to pass through the stack;
forming a slit configured to pass through the stack and the first slit insulating layer, the slit including a first region configured to intersect with the first slit insulating layer, and a second region configured not to intersect with the first slit insulating layer and having a shape such that formation of a seam is restricted to the second region or a position of the seam is controlled to the second region; and
forming a second slit insulating layer in the slit.

19. The method according to claim 18 , wherein the second region has a width greater than a width of the first region.

Assignees

• Sk Hynix Inc

Inventors

• Kim Tae Kyung
• Park Chul Young
• Yune Hyoung Soon

Classifications

• H10W20/089

  using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning · CPC title

• H10W20/082

  the openings being tapered via holes · CPC title

• H10W20/056

  by filling conductive material into holes, grooves or trenches · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H10W20/435 Primary

  Cross-sectional shapes or dispositions of interconnections · CPC title