Nonvolatile semiconductor memory device

Patent metadata

Field	Value
Publication number	US-8969945-B2
Application number	US-201313848248-A
Country	US
Kind code	B2
Filing date	Mar 21, 2013
Priority date	Sep 5, 2012
Publication date	Mar 3, 2015
Grant date	Mar 3, 2015

Abstract

According to one embodiment, a nonvolatile semiconductor memory device, includes: a stacked body including a plurality of electrode layers stacked alternately with a plurality of insulating films; a plurality of first channel body layers; a memory film; a plurality of selection gates; a second channel body layer connecting to each of the plurality of first channel body layers; a gate insulating film; and a first interconnect electrically connected to at least one of the plurality of electrode layers. The stacked body has a through-hole communicating from the upper surface of the stacked body to the lower surface of the stacked body outside a cell region. And the first interconnect is drawn out through the through-hole from the upper surface side of the stacked body to the lower surface side of the stacked body.

First claim

What is claimed is:

1. A nonvolatile semiconductor memory device, comprising:
a foundation layer;
a stacked body provided on the foundation layer, the stacked body including a plurality of electrode layers stacked alternately with a plurality of insulating films;
a plurality of first channel body layers piercing the stacked body, and the plurality of first channel body layers extending from an upper surface of the stacked body to a lower surface of the stacked body;
a memory…

Assignees

• Toshiba Kk

Inventors

• Kito Masaru
• Hishida Tomoo
• Fukuzumi Yoshiaki

Classifications

• H10D30/693 Primary

  Electricity · mapped topic

• H10D30/69 Primary

  Electricity · mapped topic

• H01L27/11582

  Electricity · mapped topic

• H01L29/792 Primary

  Electricity · mapped topic

• H01L27/11575

  Electricity · mapped topic