Wiring substrate and method for manufacturing wiring substrate

Patent metadata

Field	Value
Publication number	US-11729912-B2
Application number	US-202117388134-A
Country	US
Kind code	B2
Filing date	Jul 29, 2021
Priority date	Aug 6, 2020
Publication date	Aug 15, 2023
Grant date	Aug 15, 2023

Abstract

A wiring substrate includes an insulating layer including inorganic fillers and resin, and a conductor layer formed on a surface of the insulating layer and having a conductor pattern. The surface of the insulating layer has an arithmetic average roughness Ra in the range of 0.05 μm to 0.5 μm, the conductor layer includes a metal film formed on the surface of the insulating layer, and the inorganic fillers include a first inorganic filler including particles such that each of the particles has a portion of a surface separated from the resin and forming a gap with respect to the resin of the insulating layer and that the metal film of the conductor layer includes part formed in the gap between the first inorganic filler and the resin.

First claim

What is claimed is:

1. A wiring substrate, comprising:
an insulating layer comprising a plurality of inorganic fillers and resin; and
a conductor layer formed on a surface of the insulating layer and having a conductor pattern,
wherein the surface of the insulating layer has an arithmetic average roughness Ra in a range of 0.05 μm to 0.5 μm, the conductor layer includes a metal film formed on the surface of the insulating layer, the plurality of inorganic fillers includes a first inorganic filler comprising particles such that each of the particles has a portion of a surface separated from the resin and forming a gap with respect to the resin of the insulating layer and that the metal film of the conductor layer includes part formed in the gap between the first inorganic filler and the resin, and the conductor pattern of the conductor layer includes a wiring pattern formed such that a combination L/S of a minimum wiring width L and a minimum wiring interval S of the wiring pattern has the minimum wiring width L in a range of 3 μm to 20 μm and the minimum wiring interval S in a range of 3 μm to 20 μm.

2. The wiring substrate according to claim 1 , wherein the surface of the insulating layer includes a region in which 5 or more of the particles of the first inorganic filler are present per 10 μm.

3. The wiring substrate according to claim 2 , wherein the metal film is an electroless plating film.

4. The wiring substrate according to claim 2 , wherein the insulating layer is formed such that a content rate of the plurality of inorganic fillers is in a range of 30% to 80%.

5. The wiring substrate according to claim 2 , wherein the insulating layer is formed such that the surface of the insulating layer includes recesses recessed toward an opposite side with respect to the metal film and that the particles of the first inorganic filler are at least partially in the recesses.

6. The wiring substrate according to claim 1 , wherein the metal film is an electroless plating film.

7. The wiring substrate according to claim 6 , wherein the insulating layer is formed such that a content rate of the plurality of inorganic fillers is in a range of 30% to 80%.

8. The wiring substrate according to claim 6 , wherein the insulating layer is formed such that the surface of the insulating layer includes recesses recessed toward an opposite side with respect to the metal film and that the particles of the first inorganic filler are at least partially in the recesses.

9. The wiring substrate according to claim 1 , wherein the insulating layer is formed such that a content rate of the plurality of inorganic fillers is in a range of 30% to 80%.

10. The wiring substrate according to claim 9 , wherein the insulating layer is formed such that the surface of the insulating layer includes recesses recessed toward an opposite side with respect to the metal film and that the particles of the first inorganic filler are at least partially in the recesses.

11. The wiring substrate according to claim 1 , wherein the insulating layer is formed such that the surface of the insulating layer includes recesses recessed toward an opposite side with respect to the metal film and that the particles of the first inorganic filler are at least partially in the recesses.

12. A method for manufacturing a wiring substrate, comprising:
forming an insulating layer comprising a plurality of inorganic fillers and resin;
roughening a surface of the insulating layer such that the surface has an arithmetic average roughness Ra in a range of 0.05 μm to 0.5 μm; and
forming a conductor layer comprising a metal film on the surface of the insulating layer,
wherein the roughening of the surface of the insulating layer includes forming a first inorganic filler comprising particles such that each of the particles has a portion of a surface separated from the resin and forming a gap with respect to the resin of the insulating layer, and the forming of the conductor layer includes forming the metal film on the surface of the insulating layer such that part of the metal film fills the gap formed between the first inorganic filler and the resin, and forming a conductor pattern including a wiring pattern such that a combination L/S of a minimum wiring width L and a minimum wiring interval S of the wiring pattern has the minimum wiring width L in a range of 3 μm to 20 μm and the minimum wiring interval S in a range of 3 μm to 20 μm.

13. The method for manufacturing a wiring substrate according to claim 12 , wherein the roughening of the surface of the insulating layer includes roughening the surface of insulating layer such that the surface includes a region in which 5 or more of the particles of the first inorganic filler are present per 10 μm.

14. A wiring substrate, comprising:
an insulating layer comprising a plurality of inorganic fillers and resin; and
a conductor layer formed on a surface of the insulating layer and having a conductor pattern.
wherein the surface of the insulating layer has an arithmetic average roughness Ra in a range of 0.05 μm to 0.5 μm, the conductor layer includes a metal film formed on the surface of the insulating layer, the plurality of inorganic fillers includes a first inorganic filler comprising particles such that each of the particles has a portion of a surface separated from the resin and forming a gap with respect to the resin of the insulating layer and that the metal film of the conductor layer includes part formed in the gap between the first inorganic filler and the resin, and the insulating layer is formed such that the surface of the insulating layer includes recesses recessed toward an opposite side with respect to the metal film and that the particles of the first inorganic filler are at least partially in the recesses.

15. The wiring substrate according to claim 14 , wherein the surface of the insulating layer includes a region in which 5 or more of the particles of the first inorganic filler are present per 10 μm.

16. The wiring substrate according to claim 15 , wherein the metal film is an electroless plating film.

17. The wiring substrate according to claim 15 , wherein the insulating layer is formed such that a content rate of the plurality of inorganic fillers is in a range of 30% to 80%.

18. The wiring substrate according to claim 14 , wherein the metal film is an electroless plating film.

19. The wiring substrate according to claim 18 , wherein the insulating layer is formed such that a content rate of the plurality of inorganic fillers is in a range of 30% to 80%.

20. The wiring substrate according to claim 14 , wherein the insulating layer is formed such that a content rate of the plurality of inorganic fillers is in a range of 30% to 80%.

21. A method for manufacturing a wiring substrate, comprising:
forming an insulating layer comprising a plurality of inorganic fillers and resin;
roughening a surface of the insulating layer such that the surface has an arithmetic average roughness Ra in a range of 0.05 μm to 0.5 μm; and
forming a conductor layer comprising a metal film on the surface of the insulating layer,
wherein the insulating layer is formed such that the surface of the insulating layer includes recesses recessed toward an opposite side with respect to the metal film and that the particles of the first inorganic filler are at least partially in the recesses, the roughening of the surface of the insulating layer includes forming a first inorganic filler comprising particles such that each of the particl

Assignees

• Ibiden Co Ltd

Inventors

• Ikeda Kosuke

Classifications

• H05K1/119 Primary

  Details of rigid insulating substrates therefor, e.g. three-dimensional details (H05K1/117 takes precedence) · CPC title

• H05K3/381

  by special treatment of the substrate · CPC title

• H05K1/0373 Primary

  containing additives, e.g. fillers (H05K1/036 takes precedence) · CPC title

• H05K3/108

  by semi-additive methods; masks therefor (characterised by metallic etch mask H05K3/062; electroplating methods or apparatus H05K3/241) · CPC title

• H05K2201/0344

  Electroless sublayer, e.g. Ni, Co, Cd or Ag; Transferred electroless sublayer · CPC title