Semiconductor device

Patent metadata

Field	Value
Publication number	US-11728434-B2
Application number	US-202017011221-A
Country	US
Kind code	B2
Filing date	Sep 3, 2020
Priority date	Aug 30, 2017
Publication date	Aug 15, 2023
Grant date	Aug 15, 2023

Abstract

A semiconductor device includes a first fin type pattern on a substrate, a second fin type pattern, parallel to the first fin type pattern, on the substrate, and an epitaxial pattern on the first and second fin type patterns. The epitaxial pattern may include a shared semiconductor pattern on the first fin type pattern and the second fin type pattern. The shared semiconductor pattern may include a first sidewall adjacent to the first fin type pattern and a second sidewall adjacent to the second fin type pattern. The first sidewall may include a first lower facet, a first upper facet on the first lower facet and a first connecting curved surface connecting the first lower and upper facets. The second sidewall may include a second lower facet, a second upper facet on the second lower facet and a second connecting curved surface connecting the second lower and upper facets.

First claim

What is claimed is:

1. A semiconductor device comprising:
a substrate;
a first fin type pattern disposed on the substrate;
a second fin type pattern disposed on the substrate;
a field insulation disposed on the substrate, and disposed between the first fin type pattern and the second fin type pattern;
a first gate disposed on the first fin type pattern, the second fin type pattern, and the field insulation;
a second gate disposed on the first fin type pattern, the second fin type pattern, and the field insulation; and
an epitaxial pattern disposed on the first fin type pattern and the second fin type pattern, the epitaxial pattern being included in a source/drain of a transistor,
wherein the epitaxial pattern includes:
a shared semiconductor pattern disposed on the first fin type pattern and the second fin type pattern, the shared semiconductor pattern including a curved top surface and curved sidewall surfaces, and
a capping semiconductor pattern disposed directly on the curved top surface and on the curved sidewall surfaces of the shared semiconductor pattern, the capping semiconductor pattern having a varying width, and an upper surface of the capping semiconductor pattern including a recess that includes a linear connecting portion that is parallel to a bottom of the substrate, and

wherein the capping semiconductor pattern is a single layer.

2. The semiconductor device of claim 1 , wherein the linear connecting portion of the recess of the upper surface of the capping semiconductor pattern is disposed at a center portion of the recess.

3. The semiconductor device of claim 1 , wherein:
the upper surface of the capping semiconductor pattern includes a first top portion disposed directly above the first fin type pattern and a second top portion disposed directly above the second fin type pattern, and
the recess of the upper surface of the capping semiconductor pattern is disposed between the first top portion and the second top portion, a width of the capping semiconductor pattern at each of the first and second top portions being larger than a width of the capping semiconductor pattern at a sidewall of the recess.

4. The semiconductor device of claim 1 , wherein the recess of the upper surface of the capping semiconductor pattern has a cross-section of a truncated V-shape.

5. The semiconductor device of claim 1 , wherein an upper surface of the shared semiconductor pattern includes a curved concave region that vertically overlaps with the recess of the upper surface of the capping semiconductor pattern.

6. The semiconductor device of claim 1 , further comprising a contact disposed on the epitaxial pattern.

7. The semiconductor device of claim 1 , wherein the capping semiconductor pattern covers sidewalls of the shared semiconductor pattern, and overlaps at least some of an upper surface of the shared semiconductor pattern.

8. A semiconductor device comprising:
a substrate;
a first fin type pattern disposed on the substrate;
a second fin type pattern disposed on the substrate;
a field insulation disposed on the substrate, and disposed between the first fin type pattern and the second fin type pattern;
a first gate disposed on the first fin type pattern, the second fin type pattern, and the field insulation;
a second gate disposed on the first fin type pattern, the second fin type pattern, and the field insulation;
a shared semiconductor pattern on the first fin type pattern and the second fin type pattern, the shared semiconductor pattern including a curved top surface and curved sidewall surfaces, and the shared semiconductor pattern being included in a transistor that uses the first fin type pattern and the second fin type pattern as a channel; and
a capping semiconductor pattern directly on the curved top surface and on the curved sidewall surfaces of the shared semiconductor pattern, the capping semiconductor pattern having a gradually varying width along the curved sidewall surfaces of the shared semiconductor pattern, and an upper surface of the capping semiconductor pattern having a recess that includes a linear connecting portion,
wherein the capping semiconductor pattern is a single layer.

9. The semiconductor device of claim 8 , wherein an upper surface of the shared semiconductor pattern includes a curved concave region.

10. The semiconductor device of claim 8 , further comprising a contact disposed on the shared semiconductor pattern.

11. The semiconductor device of claim 8 , wherein the capping semiconductor pattern is a single layer directly on the shared semiconductor pattern, and the linear connecting portion is at a center region of the recess.

12. The semiconductor device of claim 11 , wherein the recess of the upper surface of the capping semiconductor pattern has a cross-section of a truncated V-shape.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Seok Hoon
• Kim Dong Myoung
• Shin Dong Suk
• Lee Seung Hun
• Lee Cho Eun
• Lee Hyun Jung
• Jang Sung Uk
• Cho Edward Nam Kyu
• Choi Min-Hee

Classifications

• H10P14/274

  using seed materials · CPC title

• H10P14/3411

  Silicon, silicon germanium or germanium · CPC title

• H10W20/042

  the barrier, adhesion or liner layers being seed or nucleation layers · CPC title

• H10D30/611

  having multiple independently-addressable gate electrodes influencing the same channel (FinFETs having multiple distinct gate electrodes H10D30/6215; multi-gate TFT H10D30/6733) · CPC title

• H10D30/024

  of fin field-effect transistors [FinFET] · CPC title