Semiconductor devices and methods of manufacturing the same

US9337031B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9337031-B2
Application numberUS-201414516603-A
CountryUS
Kind codeB2
Filing dateOct 17, 2014
Priority dateJan 28, 2014
Publication dateMay 10, 2016
Grant dateMay 10, 2016

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  1. Title

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  2. Abstract

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  5. First independent claim

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Abstract

Official abstract text for this publication.

A method of manufacturing a semiconductor device includes partially removing an upper portion of an active fin of a substrate loaded in a chamber to form a trench; and forming a source/drain layer in the trench, which includes providing a silicon source gas, a germanium source gas, an etching gas and a carrier gas into the chamber to perform a selective epitaxial growth (SEG) process using a top surface of the active fin exposed by the trench as a seed so that a silicon-germanium layer is grown; and purging the chamber by providing the carrier gas into the chamber to etch the silicon-germanium layer.

First claim

Opening claim text (preview).

What is claimed is: 1. A method of manufacturing a semiconductor device, the method comprising: partially removing an upper portion of an active fin of a substrate loaded in a chamber to form a trench; and forming a source/drain layer in the trench, including: providing a silicon source gas, a germanium source gas, an etching gas and a carrier gas into the chamber to perform a selective epitaxial growth (SEG) process using a top surface of the active fin exposed by the trench as a seed so that a silicon-germanium layer is grown; and purging the chamber by providing the carrier gas into the chamber to etch the silicon-germanium layer. 2. The method as claimed in claim 1 , wherein the silicon source gas includes dichlorosilane (SiH 2 Cl 2 ) gas, the germanium source gas includes germane (GeH 4 ) gas, the etching gas includes hydrogen chloride (HCl) gas, and the carrier gas includes hydrogen (H 2 ) gas. 3. The method as claimed in claim 2 , wherein a ratio of the etching gas with respect to the germanium source gas remaining in the chamber during at least an initial period of etching the silicon-germanium layer is higher than that during growing the silicon-germanium layer. 4. The method as claimed in claim 2 , wherein growing the silicon-germanium layer is performed by providing diborane (B 2 H 6 ) gas serving as a p-type impurity source gas into the chamber in addition to the silicon source gas, the germanium source gas, the etching gas and the carrier gas. 5. The method as claimed in claim 1 , wherein forming the source/drain layer includes: forming a first silicon-germanium layer; forming a second silicon-germanium layer on the first silicon-germanium layer, the second silicon-germanium layer having higher contents of germanium and boron than the first silicon-germanium layer; and forming a silicon layer on the second silicon-germanium layer, wherein forming the second silicon-germanium layer includes growing the second silicon-germanium layer and etching the second silicon-germanium layer. 6. The method as claimed in claim 1 , wherein growing the silicon-germanium layer and etching the silicon-germanium layer are each performed a plurality of times. 7. The method as claimed in claim 6 , wherein the trench is filled with the silicon-germanium layer after growing the silicon-germanium layer a plurality of times. 8. The method as claimed in claim 1 , wherein etching the silicon-germanium layer is performed at a temperature higher than that of growing the silicon-germanium layer. 9. The method as claimed in claim 1 , further comprising forming a plurality of dummy gate structures on the active fin prior to forming the trench, wherein the trench is formed by removing an upper portion of the active fin not covered by the dummy gate structures.

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What does patent US9337031B2 cover?
A method of manufacturing a semiconductor device includes partially removing an upper portion of an active fin of a substrate loaded in a chamber to form a trench; and forming a source/drain layer in the trench, which includes providing a silicon source gas, a germanium source gas, an etching gas and a carrier gas into the chamber to perform a selective epitaxial growth (SEG) process using a to…
Who is the assignee on this patent?
Samsung Electronics Co Ltd
What technology area does this patent fall under?
Primary CPC classification H10P14/3411. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue May 10 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).