Selective deposition of embedded thin-film resistors for semiconductor packaging

Patent metadata

Field	Value
Publication number	US-11728265-B2
Application number	US-201816129711-A
Country	US
Kind code	B2
Filing date	Sep 12, 2018
Priority date	Sep 12, 2018
Publication date	Aug 15, 2023
Grant date	Aug 15, 2023

Abstract

Embodiments include package substrates and a method of forming the package substrates. A package substrate includes a dielectric having a cavity that has a footprint, a resistor embedded in the cavity of the dielectric, and a plurality of traces on the resistor, where a plurality of surfaces of the resistor are activated surfaces. The resistor may also have a plurality of sidewalls which may be activated sidewalls and tapered. The dielectric may include metallization particles/ions. The resistor may include resistive materials, such as nickel-phosphorus (NiP), aluminum-nitride (AlN), and/or titanium-nitride (TiN). The package substrate may further include a first resistor embedded adjacently to the resistor. The first resistor may have a first footprint of a first cavity that is different than the footprint of the cavity of the resistor. The resistor may have a resistance value that is thus different than a first resistance value of the first resistor.

First claim

What is claimed is:

1. A package substrate, comprising:
a dielectric having a first cavity and a second cavity, wherein the first cavity has a first footprint and the second cavity has a second footprint different than the first footprint;
a first resistor embedded in the first cavity of the dielectric and a second resistor embedded in the second cavity of the dielectric, wherein each of the first resistor and the second resistor has a plurality of surfaces and a top surface, and wherein a resistance value of the first resistor is different than a resistance value of the second resistor;
a plurality of first traces on the top surface of the first resistor and a plurality of second traces on the top surface of the second resistor, wherein the plurality of surfaces of the first resistor and the second resistor are a plurality of activated surfaces; and
a plurality of routing traces on the dielectric, wherein the plurality of routing traces are adjacent to the plurality of first traces and the plurality of second traces.

2. The package substrate of claim 1 , wherein each of the first resistor and the second resistor has a plurality of sidewalls.

3. The package substrate of claim 2 , wherein the plurality of sidewalls of each of the first resistor and the second resistor are a plurality of activated sidewalls.

4. The package substrate of claim 2 , wherein the plurality of sidewalls are tapered.

5. The package substrate of claim 1 , wherein the dielectric includes at least one of a plurality of metallization particles and a plurality of metallization ions, wherein each of the first resistor and the second resistor includes one or more resistive materials, and wherein the one or more resistive materials is selected from the group consisting of nickel-phosphorus (NiP), aluminum-nitride (AlN), or titanium-nitride (TiN).

6. The package substrate of claim 1 , wherein the plurality of traces are located on the outer periphery of the top surface of the first resistor and the second resistor.

7. The package substrate of claim 1 , further comprising a seed layer disposed between the plurality of first traces and the top surface of the first resistor and between the plurality of second traces and the top surface of the second resistor, and the seed layer is disposed between the plurality of routing traces and the dielectric.

8. A method of forming a package substrate, comprising:
forming a dielectric having a first cavity and a second cavity, wherein the first cavity has a first footprint and the second cavity has a second footprint different than the first footprint;
forming a first resistor embedded in the first cavity of the dielectric and a second resistor embedded in the second cavity of the dielectric, wherein each of the first resistor and the second resistor has a plurality of surfaces and a top surface, and wherein a resistance value of the first resistor is different than a resistance value of the second resistor;
forming a plurality of first traces on the top surface of the first resistor and a plurality of second traces on the top surface of the second resistor, wherein the plurality of surfaces of the first resistor and the second resistor are a plurality of activated surfaces; and
forming a plurality of routing traces on the dielectric, wherein the plurality of routing traces are adjacent to the plurality of first traces and the plurality of second traces.

9. The method of claim 8 , wherein each of the first resistor and the second resistor has a plurality of sidewalls, wherein the plurality of sidewalls of each of the first resistor and the second resistor are a plurality of activated sidewalls, and wherein the plurality of sidewalls are tapered.

10. The method of claim 8 , wherein the dielectric includes at least one of a plurality of metallization particles and a plurality of metallization ions.

11. The method of claim 8 , wherein forming the first resistor in the first cavity of the dielectric and forming the second resistor in the second cavity of the dielectric, further includes:
patterning the dielectric to form the first cavity and the second cavity and activating the dielectric to form the activated surfaces within the first cavity and the second cavity, wherein the activated surfaces are disposed within the first cavity and the second cavity;
disposing one or more resistive materials on the activated surfaces and within the first cavity and the second cavity to form the first resistor and the second cavity resistor, wherein the one or more resistive materials is selected from the group consisting NiP, AlN, or TiN;
disposing a seed layer on the top surface of the dielectric and an exposed surface of the resistive material, wherein the seed layer includes a titanium-copper seed layer;
disposing a photoresist layer on the seed layer; and
patterning the photoresist layer over the seed layer to form one or more openings that expose one or more surfaces of the seed layer.

12. The method of claim 11 , wherein forming the plurality of first traces on the first resistor and forming the plurality of second traces on the second resistor, further includes:
disposing a conductive material into the openings to form the plurality of first traces and the plurality of second traces on the resistive material, and the plurality of routing traces on the dielectric;
removing the photoresist layer to expose the seed layer; and
etching the exposed seed layer.

13. The method of claim 8 , wherein the plurality of traces are located on the outer periphery of the top surface of the first resistor and the second resistor.

14. The method of claim 8 , further comprising:
disposing a seed layer between the plurality of first traces and the top surface of the first resistor and between the plurality of second traces and the top surface of the second resistor; and
disposing the seed layer between the plurality of routing traces and the dielectric.

15. A package substrate, comprising:
a dielectric having a cavity, wherein the cavity has a footprint;
a resistor embedded in the cavity of the dielectric, wherein the resistor has a plurality of surfaces and a top surface;
a plurality of traces on the resistor, wherein the plurality of surfaces of the resistor are a plurality of activated surfaces;
a plurality of routing traces on the dielectric, wherein the plurality of routing traces are adjacent to the plurality of traces;
a first resistor embedded in a first cavity of the dielectric, wherein the first resistor has a plurality of first surfaces and a top first surface; and
a plurality of first traces on the first resistor, wherein the plurality of first surfaces of the first resistor are a plurality of first activated surfaces, wherein the first cavity has a first footprint, wherein the first footprint of the first cavity is different than the footprint of the cavity, and wherein a resistance value of the resistor is thus different than a first resistance value of the first resistor.

Assignees

• Intel Corp

Inventors

• Marin Brandon C
• Truong Frank
• Balasubramanian Shivasubramanian
• Seneviratne Dilan
• Li Yonggang
• Paital Sameer
• Grujicic Darko
• Shanmugam Rengarajan
• Wette Melissa
• Pietambaram Srinivas

Classifications

• H10W72/90

  Bond pads, in general · CPC title

• H10W70/60

  Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) · CPC title

• H10W70/05

  of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04) · CPC title

• H10W44/401

  Resistive arrangements (H10W44/20, H10W42/80 take precedence) · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title