Method of forming patterns, integrated circuit device, and method of manufacturing the integrated circuit device

Patent metadata

Field	Value
Publication number	US-11728167-B2
Application number	US-202217680996-A
Country	US
Kind code	B2
Filing date	Feb 25, 2022
Priority date	Jun 26, 2019
Publication date	Aug 15, 2023
Grant date	Aug 15, 2023

Abstract

A hardmask structure including a plurality of hardmask layers is formed on a target layer in a first area and a second area, a first photoresist pattern in the first area and a second photoresist pattern in the second area are formed, a reversible hardmask pattern including a plurality of openings is formed by transferring shapes of the first and second photoresist patterns to a reversible hardmask layer that is one of the plurality of hardmask layers, a gap-fill hardmask pattern is formed by filling some of the plurality of openings formed in the first area with a gap-fill hardmask pattern material, and a feature pattern is formed in the target layer by transferring a shape of the gap-fill hardmask pattern to the target layer in the first area and a shape of the reversible hardmask pattern to the target layer in the second area.

First claim

What is claimed is:

1. A method of manufacturing an integrated circuit device, the method comprising:
forming a target layer on a substrate comprising a first area and a second area;
forming a hardmask structure comprising a plurality of hardmask layers on the target layer in the first area and the second area;
forming a photoresist layer on the hardmask structure in the first area and the second area;
forming a photoresist pattern by exposing and developing the photoresist layer in the first area and the second area;
forming a first hard mask pattern including a plurality of openings in the first area and the second area by transferring a shape of the photoresist pattern onto a first hardmask layer that is one of the plurality of hardmask layers, the first hardmask pattern comprising a negative hardmask pattern in the first area and a first positive hardmask pattern in the second area;
forming a second positive hardmask pattern in the first area by filling openings of the negative hardmask pattern in the first area with a second positive hardmask pattern material;
removing the negative hardmask pattern in the first area; and
forming a feature pattern from the target layer by transferring the shapes of the first and second positive hardmask patterns to the target layer.

2. The method of claim 1 , wherein
the feature pattern comprises a first pattern in the first area and a second pattern in the second area,
the first pattern has a first density of the feature pattern, and
the second pattern has a second density of the feature pattern, the second density being smaller than the first density.

3. The method of claim 1 , wherein
the feature pattern comprises a first pattern in the first area and a second pattern in the second area,
the first pattern comprises a plurality of island patterns that are apart from each other and arranged in a regular order, and
the second pattern comprises a plurality of line patterns that have different widths and different lengths and are apart from each other with different distances therebetween.

4. The method of claim 1 , wherein the first positive hardmask pattern and the second positive hardmask pattern include different materials from each other.

5. The method of claim 1 , wherein
the plurality of hardmask layers comprise a first bottom hardmask layer, a second bottom hardmask layer, and a main hardmask layer, which are sequentially stacked between the target layer and the first hardmask layer, and
each of the first bottom hardmask layer, the second bottom hardmask layer, and the main hardmask layer includes a different material which has different etching selectivity from other materials of neighboring layers at its bottom and top.

6. The method of claim 1 , wherein
the plurality of hardmask layers comprise a main hardmask layer, the main hardmask layer has a top surface contacting a first bottom of the first positive hardmask pattern and contacting a second bottom of the second positive hardmask pattern,
the main hardmask layer includes a polysilicon layer,
the first positive hardmask pattern includes a silicon oxide layer, and
the second positive hardmask pattern includes a spin on hardmask (SOH) layer.

7. The method of claim 1 , wherein, in the forming of the second positive hardmask pattern, the second positive hardmask pattern is formed by filling an SOH material including an organic compound in the openings of the negative hardmask pattern by using a spin coating process.

8. The method of claim 1 , wherein, in the forming of the photoresist pattern, the photoresist layer is exposed to an extreme ultraviolet (EUV) light pattern and developed simultaneously in the first area and the second area.

9. A method of manufacturing an integrated circuit device, the method comprising:
forming a target layer on a substrate comprising a cell array area and a peripheral circuit area;
forming a hardmask structure comprising a plurality of hardmask layers on the target layer in the cell array area and the peripheral circuit area;
forming a photoresist pattern in the cell array area and the peripheral circuit area, the photoresist pattern including a first photoresist pattern in the cell array area and a second photoresist pattern in the peripheral circuit area, the first photoresist pattern and the second photoresist pattern have a different planar shape from each other;
forming a first hard mask pattern in the cell array area and the peripheral circuit area by transferring a shape of the photoresist pattern onto a first hardmask layer that is one of the plurality of hardmask layers, the first hardmask pattern comprising a negative hardmask pattern having first openings in the cell array area and a first positive hardmask pattern having second openings in the peripheral circuit area;
forming a second positive hardmask pattern in the cell array area, the second positive hardmask pattern filling the first openings of the negative hardmask pattern;
removing the negative hardmask pattern in the cell array area; and
forming a feature pattern in the cell array area and the peripheral circuit area by transferring shapes the first and second positive hardmask patterns to the target layer.

10. The method of claim 9 , wherein the first photoresist pattern includes a plurality of holes, and the second photoresist pattern includes a plurality of line patterns.

11. The method of claim 9 , wherein
the feature pattern comprises a first pattern in the cell array area and a second pattern in the peripheral circuit area, and
a first density of the first pattern is greater than a second density of the second pattern.

12. The method of claim 9 , wherein the first positive hardmask pattern and the second positive hardmask pattern include different materials from each other.

13. The method of claim 9 , wherein
the plurality of hardmask layers comprise a first bottom hardmask layer, a second bottom hardmask layer, and a main hardmask layer, which are sequentially stacked between the target layer and the first hardmask layer, and
each of the first bottom hardmask layer, the second bottom hardmask layer, and the main hardmask layer includes a different material which has different etching selectivity from other materials of neighboring layers at its bottom and top.

14. The method of claim 9 , wherein the plurality of hardmask layers comprise a main hardmask layer having a top surface contacting a first bottom of the first positive hardmask pattern and a second bottom of the second positive hardmask pattern.

15. The method of claim 9 , wherein
the plurality of hardmask layers comprise a main hardmask layer,
the main hardmask layer comprises a polysilicon layer,
the first positive hardmask pattern comprises a silicon oxide layer having a bottom surface contacting the polysilicon layer, and
the second positive hardmask pattern comprises a spin on hardmask (SOH) layer having a bottom surface contacting the polysilicon layer.

16. A method of manufacturing an integrated circuit device, the method comprising:
forming a target layer on a substrate comprising a cell array area and a peripheral circuit area;
forming a hardmask structure on the target layer in the cell array area and the peripheral circuit area, wherein the hardmask structure includes a first bottom hardmask layer, a second bottom hardmask layer, a main hardmask layer, a reversible hardmask layer, and a top hardmask layer, which are sequentially stacked on the target layer;
forming a photoresist pattern in the cell array area and the peripheral circuit area, the photoresist pattern includin

Assignees

• Samsung Electronics Co Ltd

Inventors

• Lee Dongjun
• Kim Keunnam
• Kim Daehyoun
• Park Taejin
• Han Sunghee

Classifications

• H10W20/0633

  using subtractive patterning of the conductive members · CPC title

• H10P76/204

  of organic photoresist masks · CPC title

• H10P50/73

  using masks for insulating materials · CPC title

• H10W20/089

  using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning · CPC title

• H10W20/063

  by forming conductive members before forming protective insulating material · CPC title