Method for forming patterns of a semiconductor device

Patent metadata

Field	Value
Publication number	US-10224213-B2
Application number	US-201715444381-A
Country	US
Kind code	B2
Filing date	Feb 28, 2017
Priority date	Apr 28, 2016
Publication date	Mar 5, 2019
Grant date	Mar 5, 2019

Abstract

A method for forming patterns of a semiconductor device includes sequentially forming a hard mask layer, a sacrificial layer, and an anti-reflection layer on a substrate, the substrate including a cell region and a peripheral circuit region, patterning the sacrificial layer to form a first sacrificial pattern on the cell region and a second sacrificial pattern on the peripheral circuit region, forming spacers covering sidewalls of the first and second sacrificial patterns, and removing the first sacrificial pattern. The anti-reflection layer includes a lower anti-reflection layer and an upper anti-reflection layer which are formed of materials different from each other. In the patterning of the sacrificial layer, the anti-reflection layer is patterned to form a first anti-reflection pattern on the first sacrificial pattern and a second anti-reflection pattern on the second sacrificial pattern. The second anti-reflection pattern remains when the first sacrificial pattern is removed.

First claim

What is claimed is:

1. A method for forming patterns of a semiconductor device, the method comprising:
sequentially forming a hard mask layer, a sacrificial layer, and an anti-reflection layer on a substrate, the substrate including a cell region and a peripheral circuit region;
patterning the sacrificial layer to form, a first sacrificial pattern on the cell region and a second sacrificial pattern on the peripheral circuit region;
forming spacers covering sidewalls of the first and second sacrificial patterns; and
removing the first sacrificial pattern,
wherein the anti-reflection layer comprises:
a lower anti-reflection layer and an upper anti-reflection layer which are formed of materials different from each other,
wherein, in the patterning of the sacrificial layer, the anti-reflection layer is patterned, to form a first anti-reflection pattern on the first sacrificial pattern and a second anti-reflection pattern on the second sacrificial pattern, and
wherein the second anti-reflection pattern, remains when the first sacrificial pattern is removed,
wherein the spacers and the lower anti-reflection layer include silicon oxide or a nitride, and
when the spacers and the lower anti-reflection layer include silicon oxide, the upper anti-reflection layer includes silicon nitride, boron nitride, or titanium nitride, and when the spacers and the lower anti-reflection layer include a nitride, the upper anti-reflection layer includes silicon oxide.

2. The method of claim 1 , wherein an etch rate of the upper, anti-reflection layer is lower than an etch rate of the spacers.

3. The method of claim 1 , wherein the first anti-reflection pattern comprises a first lower anti-reflection pattern formed by patterning the lower anti-reflection layer, and
wherein the second anti-reflection pattern comprises:
a second lower anti-reflection pattern formed by patterning the lower anti-reflection layer; and
an upper anti-reflection pattern formed by patterning the upper anti-reflection layer.

4. The method of claim 3 , wherein the first lower anti-reflection pattern is removed when the spacers are formed.

5. The method of claim 1 , wherein the first anti-reflection pattern comprises:
a first lower anti-reflection pattern formed by patterning the lower anti-reflection layer; and
a first upper anti-reflection pattern formed by patterning the upper anti-reflection layer, and
wherein the second anti-reflection pattern comprises:
a second lower anti-reflection pattern formed by patterning the lower anti-reflection layer; and
a second upper anti-reflection pattern formed by patterning the upper anti-reflection layer.

6. The method of claim 1 , wherein a width of the second sacrificial pattern of the peripheral circuit region is greater than a width of the first sacrificial pattern of the cell region.

7. The method of claim 1 , further comprising:
etching the hard mask layer using the spacers of the cell region as etch masks to form first hard mask patterns; and
etching the hard mask layer using the second sacrificial pattern and the spacers of the peripheral circuit region as etch masks to form a second hard mask pattern.

8. A method for forming patterns of a semiconductor device, the method comprising:
sequentially forming a hard mask layer, a sacrificial layer, an anti-reflection layer, and a protection layer on a substrate, the substrate including a cell region and a peripheral circuit region;
patterning the anti-reflection layer and the sacrificial layer to form a first sacrificial pattern and a first anti-reflection pattern on the cell region and to form a second sacrificial pattern and a second anti-reflection pattern on the peripheral circuit region;
forming spacers covering sidewalk of the first and second sacrificial patterns;
removing the first sacrificial pattern;
etching the hard mask layer using the spacers of the cell region as etch masks to form first hard mask patterns; and
etching the hard mask layer using the second sacrificial pattern and the spacers of the peripheral circuit region as etch masks to form a second hard mask pattern,
wherein the protection layer is etched to form a first protection pattern on the second anti-reflection pattern during the patterning of the anti-reflection layer and the sacrificial layer,
wherein the first protection pattern remains when the first sacrificial pattern is removed,
wherein the anti-reflection layer and the protection layer overlap each other,
wherein the spacers include silicon oxide,
wherein the anti-reflection layer includes SiO x N 1-x ,
wherein the protection layer is SiO 1-y N y , and
wherein “x” is equal to or greater than 0.9 and less than 1, and “y” is equal to or greater than 0.9 and less than 1.

9. The method of claim 8 , wherein a rate by which the protection layer is etched is greater than a rate by which the spacers are etched.

10. The method of claim 8 , wherein the protection layer is etched to form a second protection pattern on the first anti-reflection pattern when the anti-reflection layer and the sacrificial layer are patterned,
wherein the second protection pattern has a first thickness, and
wherein the first protection pattern has a second thickness greater than the first thickness.

11. The method of claim 10 , wherein the first anti-reflection pattern and the second protection pattern are removed when the spacers are formed.

12. A method for forming patterns of a semiconductor device, the method comprising:
sequentially forming a first hard mask layer, a sacrificial layer, a lower anti-reflection layer and an upper anti-reflection layer on a substrate, the substrate including a cell region and a peripheral circuit region;
patterning the sacrificial layer and the lower and upper anti-reflection layers to form a first sacrificial pattern on the cell region and a second sacrificial pattern on the peripheral circuit region, wherein, when patterning the sacrificial layer and the lower and upper anti-reflection layers, the upper anti-reflection layer is etched by a first degree in the cell region, and the upper anti-reflection layer is etched by a second degree, smaller than the first degree, in the peripheral circuit region to remain in the peripheral circuit region;
forming a pair of first spacers on opposing sidewalls of the first sacrificial pattern and a pair of second spacers on opposing sidewalls of the second sacrificial pattern;
removing the first sacrificial pattern; and
patterning the first hard mask layer using the pair of first spacers, the pair of second spacers and the second sacrificial pattern to form a first mask pattern on the cell region and a second mask pattern on the peripheral circuit region,
wherein at least one spacer of the pair of first spacers or the pair of second spacers includes a nitride,
wherein the lower anti-reflection layer includes SiO 1-z N z ,
wherein the upper anti-reflection layer includes SiO w N 1-w , and
wherein “z” is equal to or greater than 0.9 and less than 1, and “w” is equal to or greater than 0.9 and less than 1.

13. The method of claim 12 , wherein, when patterning the sacrificial layer and the lower and upper anti-reflection layers, the upper anti-reflection layer remains in the cell region, and
wherein the upper anti-reflection layer that remains in the cell region has a smaller thickness than the upper anti-reflection layer that remains in the peripheral circuit region.

14. The method of claim 12 , wherein, when patterning the sacrificial layer and the lower and upper anti-reflection layers, the upper anti-reflection layer is removed from the cell region.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Byun Kyungmun
• DO Sinhae
• Im Badro

Classifications

• H10P76/4085 Primary

  characterised by the processes involved to create the masks · CPC title

• H01L21/32139

  Electricity · mapped topic

• H01L21/28017

  Electricity · mapped topic

• H01L21/3086 Primary

  Electricity · mapped topic

• G03F1/46

  Antireflective coatings · CPC title