Fully-differential preamplifier

Patent metadata

Field	Value
Publication number	US-11722108-B2
Application number	US-202117538837-A
Country	US
Kind code	B2
Filing date	Nov 30, 2021
Priority date	Nov 30, 2021
Publication date	Aug 8, 2023
Grant date	Aug 8, 2023

Abstract

Described herein is a fully-differential preamplifier comprising an input differential pair, an output current load, and a current source. The current source is coupled between the input differential pair and a low voltage rail and configured to control whether the fully-differential preamplifier is operating in a first mode or a second mode, wherein the preamplifier draws more current when operating in the second mode compared to when operating in the first mode. The input differential pair is coupled between the output current load and the current source. The output current load is coupled between a high voltage rail and the input differential pair. The input differential pair comprise positive and negative inputs of the fully-differential preamplifier. Nodes where the input differential pair and the output current load are coupled to one another comprise positive and negative outputs of the fully-differential preamplifier.

First claim

What is claimed is:

1. A fully-differential preamplifier having a differential pair of inputs including a positive input and a negative input, and a differential pair of outputs including a positive output and a negative output, the fully-differential preamplifier comprising:
first and second N-channel metal-oxide-semiconductor field-effect transistors (MOSFETs), and first and second P-channel MOSFETs, each of which includes a gate, a drain, and a source;
the sources of first and second N-channel MOSFETs connected to one another;
the sources of the first and second P-channel MOSFETs connected to one another and to a high voltage rail;
a current source connected between the connected together sources of the first and second N-channel MOSFETs and a low voltage rail;
the gate of the first N-channel MOSFET comprising the positive input of the fully-differential preamplifier;
the gate of the second N-channel MOSFET comprising the negative input of the fully-differential preamplifier;
the drains of the first N-channel MOSFET and the first P-channel MOSFET connected to one another and comprising the negative output of the fully-differential preamplifier;
the drains of the second N-channel MOSFET and the second P-channel MOSFET connected to one another and comprising the positive output of the fully-differential preamplifier;
a first resistor and a first switch connected in parallel with one another between the gate and the drain of the first N-channel MOSFET;
a second resistor and a second switch connected in parallel with one another between the gate and the drain of the second N-channel MOSFET;
a third resistor and a third switch connected in parallel with one another between the gate and the drain of the first P-channel MOSFET; and
a fourth resistor and a fourth switch connected in parallel with one another between the gate and the drain of the second P-channel MOSFET;
wherein the first, second, third and fourth switches are configured to reset an operating voltage of the fully-differential preamplifier when the first, second, third, and fourth switches are simultaneously closed for a period of time.

2. The fully-differential preamplifier of claim 1 , further comprising:
a first capacitor coupled between the gate and the source of the first P-channel MOSFET; and
a second capacitor coupled between the gate and the source of the second P-channel MOSFET;
wherein the first and second capacitors are configured to maintain voltages at the gates of the first and second P-channel MOSFETs so that the first and second P-channel MOSFETs act as current sources and increase an impedance of the fully-differential preamplifier, compared to if the first and second capacitors were not present.

3. The fully-differential preamplifier of claim 2 , wherein the differential pair of inputs of fully-differential preamplifier, which include the positive input and the negative input, are configured to be coupled to a pair of electrodes of an implantable medical device (IMD), and further comprising:
a first high pass filter (HPF) coupled between a first one of the electrodes and the positive input; and
a second high pass filter (HPF) coupled between a second one of the electrodes and the positive input;
wherein the first and second HPFs are configured to filter out one or more signals indicative of cardiac electrical activity that may be sensed by the pair of electrodes.

4. The fully-differential preamplifier of claim 3 , wherein:
the first HPF comprises a third capacitor and a fifth resistor, the third capacitor including a first terminal and a second terminal, the first terminal of the third capacitor coupled to the first one of the electrodes, and the fifth resistor coupled between the second terminal of the third capacitor and the low voltage rail; and
the second HPF comprises a fourth capacitor and a sixth resistor, the fourth capacitor including a first terminal and a second terminal, the first terminal of the fourth capacitor coupled to the second one of the electrodes, and the sixth resistor coupled between the second terminal of the fourth capacitor and the low voltage rail.

5. The fully-differential preamplifier of claim 4 , further comprising:
a fifth switch connected in parallel with the fifth resistor between the second terminal of the third capacitor and the low voltage rail; and
a sixth switch connected in parallel with the sixth resistor between the second terminal of the fourth capacitor and the low voltage rail;
wherein the fifth and sixth switches are configured to force a zero voltage differential between the positive input and the negative input, when the third and fourth switches are simultaneously closed.

6. The fully-differential preamplifier of claim 5 , wherein the fully-differential preamplifier is configured for inclusion within a fully-differential receiver, and wherein the fifth and sixth switches when closed are configured to blank the fully-differential receiver.

7. The fully-differential preamplifier of claim 5 , further comprising:
a fifth capacitor coupled between the second terminal of the third capacitor and the negative input; and
a sixth capacitor coupled between the second terminal of the fourth capacitor and the negative input;
wherein the fifth and sixth capacitors comprise direct current (DC) blocking capacitors.

8. The fully-differential preamplifier of claim 1 , wherein the current source is configured to change operation of the fully-differential preamplifier from a low current mode to a higher current mode in response to a mode control signal received from a controller.

9. The fully-differential preamplifier of claim 1 , further comprising:
a pair of blanking switches that are configured to force a zero voltage differential between the positive and negative inputs, in response to the blanking switches being simultaneously closed.

10. The fully-differential preamplifier of claim 9 , wherein a voltage differential between the positive and negative outputs is substantially zero while the pair of blanking switches are both closed.

11. A fully-differential preamplifier, comprising:
an input differential pair, an output current load, and a current source;
the current source coupled between the input differential pair and a low voltage rail and configured to control whether the fully-differential preamplifier is operating in a first mode or a second mode, wherein the fully-differential preamplifier draws more current when operating in the second mode compared to when operating in the first mode;
the input differential pair coupled between the output current load and the current source; and
the output current load coupled between a high voltage rail and the input differential pair;
wherein the input differential pair comprise positive and negative inputs of the fully-differential preamplifier;
wherein nodes where the input differential pair and the output current load are coupled to one another comprise positive and negative outputs of the fully-differential preamplifier;
wherein the input differential pair includes first and second N-channel metal-oxide-semiconductor field-effect transistors (MOSFETs), each of which includes a gate, a drain, and a source;
wherein the output current load includes first and second P-channel MOSFETs, each of which includes a gate, a drain, and a source;
wherein the sources of the first and second P-channel MOSFETs are connected to one another and to the high voltage rail;
wherein the drain of the first P-channel MOSFET is coupled to the drain of the first N-channel MOSFET and also comprises the negative output of the fully-differential preamplifier; and
wherein the drain of the second P-channel MOSFET is cou

Assignees

• Pacesetter Inc

Inventors

• Labbe Eric C
• Persson Benjamin T

Classifications

• H03F3/45179 Primary

  using MOSFET transistors as the active amplifying circuit (H03F3/45278 takes precedence) · CPC title

• H03F3/45632

  in differential amplifiers with FET transistors as the active amplifying circuit (H03F3/4578 takes precedence) · CPC title

• H03F2203/45022

  One or more added resistors to the amplifying transistors in the differential amplifier · CPC title

• H03F2203/45026

  One or more current sources are added to the amplifying transistors in the differential amplifier · CPC title

• H03F2203/45072

  the common mode voltage or current signal being added to the tail circuit of the differential amplifier · CPC title