Differential amplifier circuit

Patent metadata

Field	Value
Publication number	US-9148098-B2
Application number	US-201314027824-A
Country	US
Kind code	B2
Filing date	Sep 16, 2013
Priority date	Apr 17, 2013
Publication date	Sep 29, 2015
Grant date	Sep 29, 2015

Abstract

A differential amplifier circuit includes a differential amplification unit suitable for amplifying difference between signals of an input terminal and a complementary input terminal, receiving the same voltage level through the input terminal and the complementary input terminal at a measurement period, and receiving an input signal and a complementary input signal through the input terminal and the complementary input terminal, respectively, at an operation period, an offset control unit suitable for generating offset information using an output of the differential amplification unit at the measurement period, and an offset compensation unit suitable for compensating for an offset of the differential amplification unit in response to the offset information.

First claim

What is claimed is:

1. A differential amplifier circuit comprising:
an input terminal suitable for receiving a preset voltage at a measurement period and receiving an input signal at an operation period;
a complementary input terminal suitable for receiving the preset voltage at the measurement period and receiving a complementary input signal at the operation period;
a first pull-down element controlled by a signal of the input terminal and suitable for pull-down driving a first node using a voltage of a common source node;
a second pull-down element controlled by a signal of the complementary input terminal and suitable for pull-down driving a second node using the voltage of the common source node;
a first inverter suitable for using a pull-up voltage and a voltage of the first node as driving voltages and driving a pre-output node in response to a complementary pre-output node;
a second inverter suitable for using the pull-up voltage and a voltage of the second node as driving voltages and driving the complementary pre-output node in response to the pre-output node;
a third inverter suitable for driving an output terminal in response to the pre-output node;
a fourth inverter suitable for driving a complementary output node in response to the complementary pre-output node;
an offset control unit suitable for generating offset information using one or more signals of the output terminal and the complementary output terminal at the measurement period; and
an offset compensation unit suitable for adjusting loadings of the first and second nodes in response to the offset information.

2. The differential amplifier circuit of claim 1 , wherein the offset information comprises a first signal for increasing the loading of the first node and a second signal for increasing the loading of the second node, and
the offset control unit stores at least one of the output signal and the complementary output signal at the measurement period, and activates one of the first and second signals using the stored signal at the operation period.

3. The differential amplifier circuit of claim 2 , wherein the offset compensation unit comprises:
a first capacitor connected to the first node when the first signal is activated; and
a second capacitor connected to the second node when the second signal is activated.

4. The differential amplifier circuit of claim 1 , further comprising a reset unit suitable for resetting the pre-output node, the complementary pre-output node, the first node, and the second node in response to a clock.

5. The differential amplifier circuit of claim 4 , further comprising a third pull-down element enabled in response to the clock and suitable for pull-down driving the common source node using a ground voltage when enabled.

Assignees

• Sk Hynix Inc

Inventors

• Kim Hyung-Soo

Classifications

• H03F3/45475

  using IC blocks as the active amplifying circuit · CPC title

• H03F2203/45396

  the AAC comprising one or more switches · CPC title

• H03F2203/45616

  the IC comprising more than one switch, which are not cross coupled · CPC title

• H03F3/45183

  Long tailed pairs (H03F3/4521, H03F3/45237 take precedence) · CPC title

• H03F1/303

  using a switching device (H03F1/305, H03F3/005, H03F3/38 take precedence) · CPC title