Buffer circuit robust to variation of reference voltage signal

Patent metadata

Field	Value
Publication number	US-2016164479-A1
Application number	US-201514959195-A
Country	US
Kind code	A1
Filing date	Dec 4, 2015
Priority date	Dec 5, 2014
Publication date	Jun 9, 2016
Grant date	—

Abstract

A buffer circuit includes a first differential amplifier, second differential amplifier, third differential amplifier, and mixer. The first differential amplifier generates a positive differential signal and a negative differential signal based on an input signal and a reference voltage signal. The second differential amplifier generates a first signal based on the positive differential signal and the negative differential signal. The third differential amplifier generates a second signal having a different phase from the first signal based on the positive differential signal and the negative differential signal. The mixer outputs a signal, generated by mixing the first signal and the second signal, as an output signal.

First claim

What is claimed is:

1 . A buffer circuit comprising:
a first differential amplifier configured to generate a positive differential signal and a negative differential signal based on an input signal and a reference voltage signal; a second differential amplifier configured to generate a first signal based on the positive differential signal and the negative differential signal; a third differential amplifier configured to generate a second signal having a different phase from the first signal based on the positive differential signal and the negative differential signal; and a mixer configured to output a signal, generated by mixing the first signal and the second signal, as an output signal.

2 . The buffer circuit of claim 1 , wherein the buffer circuit maintains a difference between a duty of the output signal and a duty of the input signal within a certain range by cancelling duty variations of the positive differential signal and the negative differential signal through the mixing when a level of the reference voltage signal is varied.

3 . The buffer circuit of claim 1 , wherein a difference between a phase of the first signal and a phase of the second signal is 180 degrees.

4 . The buffer circuit of claim 1 , wherein the mixer includes:
a first inverter configured to generate an inverted second signal by inverting the second signal; and an internal mixer configured to generate the output signal by mixing the first signal and the inverted second signal.

5 . The buffer circuit of claim 1 , wherein:
the first differential amplifier includes first and second NMOS transistors, first and second resistors, and a current source, a terminal of the first resistor receives a supply voltage, the other terminal of the first resistor is connected to a first node, a terminal of the second resistor receives the supply voltage, the other terminal of the second resistor is connected to a second node, the negative differential signal is outputted from the first node, and the positive differential signal is outputted from the second node, a drain terminal of the first NMOS transistor is connected to the first node, a gate terminal of the first NMOS transistor receives the input signal, and a source terminal of the first NMOS transistor is connected to a third node, a drain terminal of the second NMOS transistor is connected to the second node, a gate terminal of the second NMOS transistor receives the reference voltage signal, and a source terminal of the second NMOS transistor is connected to the third node, and a terminal of the current source is connected to the third node and another terminal of the current source receives a ground voltage.

6 . The buffer circuit of claim 5 , wherein:
the current source includes a third NMOS transistor, and a drain terminal of the third NMOS transistor is connected to the third node, a gate terminal of the third NMOS transistor receives a bias voltage signal, and a source terminal of the third NMOS transistor receives the ground voltage.

7 . The buffer circuit of claim 1 , wherein:
the second differential amplifier includes first and second PMOS transistors, first and second NMOS transistors, and a current source, a drain terminal of the first PMOS transistor receives a supply voltage, a gate terminal of the first PMOS transistor is connected to a first node, and a source terminal of the first PMOS transistor is connected to the first node, a drain terminal of the second PMOS transistor receives the supply voltage, a gate terminal of the second PMOS transistor is connected to the first node, a source terminal of the second PMOS transistor is connected to a second node, and the first signal is outputted from the second node, a drain terminal of the first NMOS transistor is connected to the first node, a gate terminal of the first NMOS transistor receives the positive differential signal, and a source terminal of the first NMOS transistor is connected to a third node, a drain terminal of the second NMOS transistor is connected to the second node, a gate terminal of the second NMOS transistor receives the negative differential signal, and a source terminal of the second NMOS transistor is connected to the third node, and a terminal of the current source is connected to the third node and the other terminal of the current source receives a ground voltage.

8 . The buffer circuit of claim 1 , wherein:
the third differential amplifier includes first and second PMOS transistors, first and second NMOS transistors, and a current source, a drain terminal of the first PMOS transistor receives a supply voltage, a gate terminal of the first PMOS transistor is connected to a first node, and a source terminal of the first PMOS transistor is connected to the first node, a drain terminal of the second PMOS transistor receives the supply voltage, a gate terminal of the second PMOS transistor is connected to the first node, and a source terminal of the second PMOS transistor is connected to a second node, and the second signal is outputted from the second node, a drain terminal of the first NMOS transistor is connected to the first node, a gate terminal of the first NMOS transistor receives the negative differential signal, and a source terminal of the first NMOS transistor is connected to a third node, a drain terminal of the second NMOS transistor is connected to the second node, a gate terminal of the second NMOS transistor receives the positive differential signal, and a source terminal of the second NMOS transistor is connected to the third node, and a terminal of the current source is connected to the third node and the other terminal of the current source receives a ground voltage.

9 . A buffer circuit comprising:
a first differential amplifier configured to generate a positive differential signal and a negative differential signal based on an input signal and a reference voltage signal; a second differential amplifier configured to generate a first signal based on the positive differential signal and the negative differential signal, configured to drive the first signal as a first current amount when a mode signal is deactivated, configured to drive the first signal as a second current amount, which is a half of the first current amount, when the mode signal is activated; a third differential amplifier configured to stop operating when the mode signal is deactivated, configured to generate a second signal, which has the second current amount and has a different phase from the first signal, based on the positive differential signal and the negative differential signal when the mode signal is activated; and a mixer configured to output the first signal as an output signal when the mode signal is deactivated, configured to output a signal, generated by mixing the first signal and the second signal, as the output signal when the mode signal is activated.

10 . The buffer circuit of claim 9 , wherein the buffer circuit maintains a difference between a duty of the output signal and a duty of the input signal within a certain range by cancelling duty variations of the positive differential signal and the negative differential signal through the mixing when a level of the reference voltage signal is varied and the mode signal is activated.

11 . The buffer circuit of claim 9 , wherein the mixer includes:
a first inverter configured to generate an inverted second signal by inverting the second signal; and an internal mixer configured to generate the output signal by mixing the first signal and the inverted second signal.

12 . The buffer circuit of claim 11 , wherein:
the internal mixer includes an NMOS transistor, an

Assignees

• Samsung Electronics Co Ltd

Inventors

• Eom Yoon-Joo
• Bae Seung-Jun
• Moon Dae-Sik
• Park Joon-Young
• Ahn Min-Su

Classifications

• H03F3/45179 Primary

  using MOSFET transistors as the active amplifying circuit (H03F3/45278 takes precedence) · CPC title

• H03F2203/45032

  the differential amplifier amplifying transistors are multiple paralleled transistors · CPC title

• H03D7/1441 Primary

  using field-effect transistors (H03D7/145 takes precedence) · CPC title

• H03F2203/45051

  Two or more differential amplifiers cascade coupled · CPC title

• H03F2200/366

  Multiple MOSFETs are coupled in parallel · CPC title