Semiconductor layout in FinFET technologies

Patent metadata

Field	Value
Publication number	US-11720734-B2
Application number	US-202016920524-A
Country	US
Kind code	B2
Filing date	Jul 3, 2020
Priority date	Sep 6, 2017
Publication date	Aug 8, 2023
Grant date	Aug 8, 2023

Abstract

Systems, apparatuses, and methods for placing cells in an integrated circuit are described. In various embodiments, an integrated circuit is divided into many partitions. In a first set of partitions susceptible to transistor latch-up, the many transistor gate stripes are connected to one of the power rails rather than left floating. The lengths of the transistor gate stripes are shortened for well tap cells in the first partition, but increased in a second partition susceptible for poor signal integrity. One or more implant layers are formed underneath the transistor gate stripes in each of the first and second partitions to adjust an amount of protection against transistor latch-up and poor signal integrity. An electrostatic discharge transistor is included with at least one source region of multiple source regions formed in a well with a same doping polarity as the at least one source region.

First claim

What is claimed is:

1. An integrated circuit comprising:
one or more electrostatic discharge (ESD) transistors, each comprising:
two transistor gate stripes connected to a same gate terminal; and
a plurality of source regions outside an area between the two transistor gate stripes, each source region connected through a contact to a same source terminal;
wherein a first source region of the plurality of source regions is formed in a well that has a same doping polarity as the first source region; and
wherein a given ESD transistor of the one or more ESD transistors is configured to conduct a current to the plurality of source regions of the given ESD transistor, including the first source region, responsive to detecting a charge on an I/O pin.

2. The integrated circuit as recited in claim 1 , wherein at least a second source region of the plurality of source regions is formed in an area outside of the well.

3. The integrated circuit as recited in claim 1 , wherein one of the one or more ESD transistors further comprises two drain regions between the two transistor gate stripes connected through contacts to a same drain terminal that is connected to the I/O pin.

4. The integrated circuit as recited in claim 1 , wherein each of the same gate terminal and the same source terminal is connected to a given terminal.

5. The integrated circuit as recited in claim 3 , wherein the two drain regions are formed in an area outside of the well.

6. The integrated circuit as recited in claim 1 , wherein the given ESD transistor conducts current through a parasitic bipolar transistor from the I/O pin to the plurality of source regions including the first source region.

7. The integrated circuit as recited in claim 1 , wherein:
one of the one or more ESD transistors further comprises a plurality of dummy transistor gate stripes; and
one or more of the plurality of dummy transistor gate stripes is connected to a power supply to increase decoupling capacitance.

8. A method for semiconductor fabrication comprising:
forming two transistor gate stripes of an electrostatic discharge (ESD) transistor;
connecting the two transistor gate stripes to a same gate terminal;
forming a plurality of source regions of the ESD transistor outside an area between the two transistor gate stripes;
connecting the plurality of source regions through a contact to a same source terminal; and
forming a first source region of the plurality of source regions in a well that has a same doping polarity as the first source region; and
conducting, by a given ESD transistor of the one or more ESD transistors, a current to the plurality of source regions of the given ESD transistor, including the first source region, responsive to detecting a charge on an I/O pin.

9. The method as recited in claim 8 , further comprising forming at least a second source region of the plurality of source regions in an area outside of the well.

10. The method as recited in claim 8 , further comprising forming two drain regions of the ESD transistor between the two transistor gate stripes connected through contacts to a same drain terminal that is connected to the I/O pin.

11. The method as recited in claim 10 , further comprising connecting each of the same gate terminal and the same source terminal to a given terminal.

12. The method as recited in claim 10 , further comprising forming the two drain regions in an area outside of the well.

13. The method as recited in claim 8 , further comprising conducting current, by the given ESD transistor, through a parasitic bipolar transistor from the I/O pin to the plurality of source regions including the first source region.

14. The method as recited in claim 8 , further comprising:
forming a plurality of dummy transistor gate stripes of the ESD transistor; and
connecting one or more of the plurality of dummy transistor gate stripes to a power supply to increase decoupling capacitance.

Assignees

• Apple Inc

Inventors

• Farbiz Farzan
• Hoffmann Thomas
• Zhang Xin Yi

Classifications

• H10D84/854

  comprising arrangements for preventing bipolar actions between the different IGFET regions, e.g. arrangements for latchup prevention · CPC title

• H10D30/62 Primary

  Fin field-effect transistors [FinFET] · CPC title

• H10D89/601

  for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs · CPC title

• H10D84/991

  Latch-up prevention · CPC title

• H10D84/907

  CMOS gate arrays · CPC title