Method for fabricating three-dimensional memory device by thickening an epitaxial layer

Patent metadata

Field	Value
Publication number	US-11716853-B2
Application number	US-202016895410-A
Country	US
Kind code	B2
Filing date	Jun 8, 2020
Priority date	Mar 20, 2020
Publication date	Aug 1, 2023
Grant date	Aug 1, 2023

Abstract

Three-dimensional (3D) NAND memory devices and methods are provided. In one aspect, a fabrication method includes depositing a cover layer over a substrate, depositing a sacrificial layer over the cover layer, depositing a layer stack over the sacrificial layer, forming a channel layer extending through the layer stack and the sacrificial layer, performing a first epitaxial growth to deposit a first epitaxial layer on a side portion of the channel layer that is close to the substrate, removing the cover layer, and performing a second epitaxial growth to simultaneously thicken the first epitaxial layer and deposit a second epitaxial layer on the substrate. The layer stack includes first stack layers and second stack layers that are alternately stacked.

First claim

What is claimed is:

1. A method for fabricating a three-dimensional (3D) memory device, comprising:
depositing a cover layer over a substrate;
depositing a sacrificial layer over the cover layer;
depositing a layer stack over the sacrificial layer;
forming a channel layer extending through the layer stack and the sacrificial layer;
performing a first epitaxial growth after a removal of the sacrificial layer to deposit a first epitaxial layer on a side portion of the channel layer that is close to the substrate;
removing the cover layer; and
performing a second epitaxial growth to simultaneously thicken the first epitaxial layer and deposit a second epitaxial layer on the substrate, providing a cavity between the layer stack and the second epitaxial layer over the substrate.

2. The method according to claim 1 , further comprising:
before forming the channel layer, forming a functional layer extending through the layer stack and the sacrificial layer,
wherein forming the channel layer includes forming the channel layer adjacent to the functional layer.

3. The method according to claim 2 , wherein forming the functional layer includes:
forming a channel hole through the layer stack and the sacrificial layer;
forming a blocking layer on a side wall of the channel hole;
forming a storage layer on the blocking layer; and
forming a tunnel insulation layer on the storage layer.

4. The method according to claim 2 , further comprising, before performing the first epitaxial growth:
removing a portion of the functional layer that is close to the substrate to expose the side portion of the channel layer.

5. The method according to claim 1 , wherein:
the layer stack including a plurality of first stack layers and a plurality of second stack layers alternately stacked in a direction approximately perpendicular to the substrate, the method further comprising:
removing the plurality of first stack layers.

6. The method according to claim 5 , further comprising:
forming a plurality of conductor layers, the plurality of conductor layers and the plurality of second stack layers being alternately stacked in the direction approximately perpendicular to the substrate.

7. The method according to claim 1 , further comprising:
forming a gate line slit (GLS) extending through the layer stack; and
filling the GLS with a conductive material to form a conductive layer that electrically connects with the second epitaxial layer.

8. The method according to claim 1 , wherein:
the cavity further exposes a thickened portion of the first epitaxial layer between the layer stack and the second epitaxial layer.

9. A method for fabricating a three-dimensional (3D) memory device, comprising:
depositing a sacrificial layer over a substrate;
depositing a layer stack over the sacrificial layer;
forming a channel layer extending through the layer stack and the sacrificial layer;
forming a cover layer to shield the substrate, after a removal of the sacrificial layer;
performing a first epitaxial growth to deposit a first epitaxial layer on a side portion of the channel layer that is close to the substrate;
removing the cover layer; and
performing a second epitaxial growth to simultaneously thicken the first epitaxial layer and deposit a second epitaxial layer on the substrate, providing a cavity between the layer stack and the second epitaxial layer over the substrate.

10. The method according to claim 9 , further comprising:
before forming the channel layer, forming a functional layer extending through the layer stack and the sacrificial layer,
wherein forming the channel layer includes forming the channel layer adjacent to the functional layer.

11. The method according to claim 10 , wherein forming the functional layer includes:
forming a channel hole through the layer stack and the sacrificial layer;
forming a blocking layer on a side wall of the channel hole;
forming a storage layer on the blocking layer; and
forming a tunnel insulation layer on the storage layer.

12. The method according to claim 11 , further comprising, before performing the first epitaxial growth:
removing a portion of the blocking layer that is close to the substrate to expose a portion of the storage layer;
removing the portion of the storage layer to expose a portion of the tunnel insulation layer; and
removing the portion of the tunnel insulation layer to expose the side portion of the channel layer.

13. The method according to claim 9 , wherein:
the layer stack including a plurality of first stack layers and a plurality of second stack layers alternately stacked in a direction approximately perpendicular to the substrate, the method further comprising:
removing the plurality of first stack layers.

14. The method according to claim 13 , further comprising:
forming a plurality of conductor layers, the plurality of conductor layers and the plurality of second stack layers being alternately stacked in the direction approximately perpendicular to the substrate.

15. The method according to claim 9 , further comprising:
forming a gate line slit (GLS) extending through the layer stack; and
filling the GLS with a conductive material to form a conductive layer that electrically connects with the second epitaxial layer.

Assignees

• Yangtze Memory Tech Co Ltd

Inventors

• Wu Linchun
• Zhang Kun
• Zhou Wenxi
• Xia Zhiliang

Classifications

• H10B43/35 Primary

  with cell select transistors, e.g. NAND · CPC title

• H10B43/10 Primary

  characterised by the top-view layout · CPC title

• H10B43/27

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title