Single-semiconductor-layer channel in a memory opening for a three-dimensional non-volatile memory device

Patent metadata

Field	Value
Publication number	US-2016111432-A1
Application number	US-201514972618-A
Country	US
Kind code	A1
Filing date	Dec 17, 2015
Priority date	Sep 15, 2013
Publication date	Apr 21, 2016
Grant date	—

Abstract

A memory film layer is formed in a memory opening through an alternating stack of first material layers and second material layers. A sacrificial material layer is deposited on the memory film layer. Horizontal portions of the sacrificial material layer and the memory film layer at the bottom of the memory opening is removed by an anisotropic etch to expose a substrate underlying the memory opening, while vertical portions of the sacrificial material layer protect vertical portions of the memory film layer. After removal of the sacrificial material layer selective to the memory film, a doped semiconductor material layer can be formed directly on the exposed material in the memory opening and on the memory film as a single material layer to form a semiconductor channel of a memory device.

First claim

1 . A three-dimensional memory device, comprising:
a substrate having a major surface; an alternating stack of insulating material layers and control gate electrodes located over the substrate, the alternating stack having a memory opening extending through the alternating stack in a direction substantially perpendicular to the major surface; a memory film located at a peripheral region of the memory opening; and a semiconductor channel including an upper portion extending substantially perpendicular to the major surface and contacting an inner sidewall of the memory film and a lower portion contacting a single crystalline semiconductor material portion located within or on the substrate; wherein:
an outer sidewall of the upper portion of the semiconductor channel is laterally offset with respect to an outer sidewall of the lower portion of the semiconductor channel; and
the semiconductor channel does not include a substantially contiguous interface composed of grain boundaries, not contacting the memory film, and vertically extending through the semiconductor channel between a plurality of control gate electrodes.

2 . The three-dimensional memory device of claim 1 , wherein the memory film layer comprises a stack containing, from one side to another, a blocking dielectric layer, a charge storage layer, and a tunneling dielectric layer.

3 . The three-dimensional memory device of claim 1 , wherein the single crystalline semiconductor material portion is a semiconductor material portion of the substrate.

4 . The three-dimensional memory device of claim 3 , wherein a first horizontal surface of the single crystalline semiconductor material portion is in contact with a horizontal surface of the memory film, and a second horizontal surface of the single crystalline semiconductor material portion that is vertically offset with respect to the first horizontal surface is in contact with the semiconductor channel.

5 . The three-dimensional memory device of claim 1 , wherein the outer sidewall of the upper portion of the semiconductor channel extends farther outward from a geometrical center of the memory opening than the outer sidewall of the lower portion of the semiconductor channel.

6 . The three-dimensional memory device of claim 1 , wherein the outer sidewall of the lower portion of the semiconductor channel extends farther outward from a geometrical center of the memory opening than the outer sidewall of the upper portion of the semiconductor channel.

7 . The three-dimensional memory device of claim 1 , wherein the semiconductor channel contacts a bottom surface of the memory film.

8 . The three-dimensional memory device of claim 1 , further comprising a dielectric core surrounded by the memory film, wherein a first interface between the dielectric core and the upper portion of the semiconductor channel is laterally offset from a second interface between the dielectric core and the lower portion of the semiconductor channel.

9 . The three-dimensional memory device of claim 1 , wherein a lower portion of the memory film has a lesser thickness than an upper portion of the memory film that contacts the upper portion of the semiconductor channel.

10 . The three-dimensional memory device of claim 1 , wherein the lower portion of the semiconductor channel comprises a single crystalline semiconductor material pillar which is epitaxially grown on the substrate.

11 . The three-dimensional memory device of claim 10 , wherein a vertical interface between the lower portion of the semiconductor channel and an inner sidewall of the memory film laterally extends farther out from a geometrical center of the memory opening than an outer sidewall of the upper portion of the semiconductor channel.

12 . The three-dimensional memory device of claim 1 , wherein:
the substrate comprises a silicon substrate; a monolithic three dimensional NAND string in a monolithic, three dimensional array of NAND strings is located over the silicon substrate; at least one memory cell in a first device level of the three dimensional array of NAND strings is located over another memory cell in a second device level of the three dimensional array of NAND strings; and the silicon substrate contains an integrated circuit comprising a driver circuit for the at least one memory cell.

Assignees

• Sandisk Technologies Inc

Inventors

• Rabkin Peter
• Pachamuthu Jayavel
• Alsmeier Johann

Classifications

• H01L27/1157 Primary

  Electricity · mapped topic

• H01L27/11582

  Electricity · mapped topic

• H10B41/35 Primary

  with a cell select transistor, e.g. NAND · CPC title

• H10B41/27

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title

• H10B43/27

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title