Three-dimensional memory device with support structures in gate line slits and methods for forming the same

Patent metadata

Field	Value
Publication number	US-11716850-B2
Application number	US-202117170872-A
Country	US
Kind code	B2
Filing date	Feb 8, 2021
Priority date	Jun 17, 2019
Publication date	Aug 1, 2023
Grant date	Aug 1, 2023

Abstract

A method for forming a 3D memory device is provided. The method includes forming a dielectric stack including interleaved initial insulating layers and initial sacrificial layers over a substrate, and forming at least one slit structure extending vertically and laterally in the dielectric stack and dividing the dielectric stack into block regions. The at least one slit structure each includes slit openings exposing the substrate and an initial support structure between adjacent slit openings. Each block region may include interleaved insulating layers and sacrificial layers, and the initial support structure may include interleaved insulating portions and sacrificial portions. Each insulating portion and sacrificial portion may be in contact with respective insulating layers and sacrificial layers of a same level from adjacent block regions. The method also includes forming channel structures extending vertically through the dielectric stack, replacing the sacrificial layers and sacrificial portions with conductor layers and conductor portions through the at least one slit structure, and forming a source structure in each slit structure. The source structure may include an insulating spacer in each slit opening and a source contact in a respective insulating spacer.

First claim

What is claimed is:

1. A method for forming a three-dimensional (3D) memory device, comprising:
forming a dielectric stack comprising interleaved insulating layers and sacrificial layers over a substrate;
patterning the dielectric stack to form a support opening and patterning a cut opening each along a lateral direction;
forming at least one slit structure extending vertically and laterally in the dielectric stack and dividing the dielectric stack into a plurality of block regions, the at least one slit structure each comprising a plurality of slit openings exposing the substrate and an initial support structure between adjacent slit openings, the initial support structure comprising a dividing structure formed in the support opening, wherein
the cut opening extends along the lateral direction in one of the block regions and is configured to divide the one of the block regions into memory fingers;
each of the plurality of block regions comprises a portion of the interleaved insulating layers and sacrificial layers, and
the initial support structure further comprises interleaved insulating portions and sacrificial portions, each of the insulating portions and sacrificial portions being in contact with respective insulating layers and sacrificial layers of a same level from adjacent block regions;

forming a plurality of channel structures extending vertically through the dielectric stack;
replacing the sacrificial layers and the sacrificial portions with conductor layers and conductor portions, respectively, through the at least one slit structure; and
forming a source structure in each slit structure, the source structure comprising an insulating spacer in each of the plurality of slit openings and a source contact in a respective insulating spacer.

2. The method of claim 1 , wherein:
a length of the support opening is less than a length of the slit structure along the lateral direction, a bottom of the support opening being between a top and a bottom surfaces of a first insulating layer of the dielectric stack; and
forming the at least one slit structure comprises depositing a dielectric material to fill up the support opening and form the dividing structure.

3. The method of claim 2 , wherein:
forming the at least one slit structure comprises removing portions of the dielectric stack adjacent to the dividing structure along the lateral direction to form a pair of slit openings that expose the substrate, a width of each of the pair of slit openings being less than or equal to a width of the dividing structure along another lateral direction perpendicular to the lateral direction; and
the dividing structure and remaining interleaved sacrificial portions and insulating portions under the dividing structure form the initial support structure.

4. The method of claim 3 , wherein removing the portions of the dielectric stack comprises using the dividing structure as an etch mask to etch the portions of the dielectric stack adjacent to the dividing structure and retain the interleaved sacrificial portions and insulating portions under the dividing structure.

5. The method of claim 2 , wherein forming the plurality of channel structures comprises forming at least one channel structure on both sides of the dividing structure along the other lateral direction.

6. The method of claim 1 , wherein:
a length of the support opening is equal to a length of the slit structure along the lateral direction, a bottom of the support opening being between a top and a bottom surfaces of a first insulating layer of the dielectric stack; and
forming the at least one slit structure comprises depositing a dielectric material to fill up the support opening and form an initial dividing structure.

7. The method of claim 6 , wherein forming the at least one slit structure further comprises:
along the lateral direction of the initial dividing structure, removing a pair of second portions of the dielectric material adjacent to a first portion of the dielectric material to expose portions of the dielectric stack under the second portions; and
removing the exposed portions of the dielectric stack to expose the substrate and form a pair of slit openings, a width of each of the pair of slit openings being less than or equal to a width of the initial dividing structure along another lateral direction perpendicular to the lateral direction, the first portion of the dielectric material forming the dividing structure, the dividing structure and remaining interleaved sacrificial portions and insulating portions under the dividing structure forming the initial support structure.

8. The method of claim 7 , wherein removing the exposed portions of the dielectric stack comprises using the dividing structure as an etch mask to etch the portions of the dielectric stack adjacent to the dividing structure and retain the interleaved conductor portions and insulating portions under the dividing structure.

9. The method of claim 6 , wherein forming the plurality of channel structures comprises forming at least one channel structure on both sides of the initial dividing structure along the other lateral direction.

10. The method of claim 1 , further comprising forming a cut structure in at least one of the plurality of block regions, wherein the cut structure extends in parallel with the at least one slit structure and divides the at least one of the plurality of block regions into a plurality of memory fingers.

11. The method of claim 10 , wherein
the cut opening is formed in a same patterning operation that forms the support opening, the cut opening extending in parallel with the at least one slit structure, a bottom surface of the cut opening being between a top surface and a bottom surfaces of a first insulating layer; and
forming the cut structure comprises depositing a dielectric material to fill up the cut opening in a same deposition operation that fills the support opening.

12. A method for forming a three-dimensional (3D) memory device, comprising:
forming a dielectric stack of interleaved insulating layers and sacrificial layers over a substrate;
forming a dielectric structure extending along a lateral direction in the dielectric stack, the dielectric structures extending vertically into a first insulating layer;
patterning the dielectric stack using the dielectric structure as an etch mask to form a slit structure extending vertically and laterally in the dielectric stack and dividing the dielectric stack into a pair of block regions, the slit structure comprising a plurality of slit openings exposing the substrate and a plurality of initial support structure between adjacent slit openings, wherein
each of the plurality of block regions comprises a portion of the interleaved insulating layers and sacrificial layers, and
each of the plurality of initial support structure comprises interleaved insulating portions and sacrificial portions, each of the insulating portions and sacrificial portions being in contact with respective insulating layers and sacrificial layers of a same level from adjacent block regions;

forming a plurality of channel structures extending vertically through the dielectric stack;
replacing the sacrificial layers and the sacrificial portions with conductor layers and conductor portions, respectively, through the slit structure;
forming a cut structure in at least one of the block regions, the cut structure extending in parallel with the slit structure and dividing at least one of the block regions into a plurality of memory fingers; and
forming a source structure in each slit structure, the source structure comprising an insulating spacer in each of the plurality of sl

Assignees

• Yangtze Memory Tech Co Ltd

Inventors

• Huo Zongliang
• Yang Haohao
• Xu Wei
• Yan Ping
• Huang Pan
• Zhou Wenbin

Classifications

• H10B43/10 Primary

  characterised by the top-view layout · CPC title

• H10B43/35

  with cell select transistors, e.g. NAND · CPC title

• H10B43/27 Primary

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title

• H10B43/50 Primary

  characterised by the boundary region between the core and peripheral circuit regions · CPC title