Method for fabricating semiconductor package

Patent metadata

Field	Value
Publication number	US-11715645-B2
Application number	US-202217656695-A
Country	US
Kind code	B2
Filing date	Mar 28, 2022
Priority date	Feb 14, 2020
Publication date	Aug 1, 2023
Grant date	Aug 1, 2023

Abstract

A method for fabricating a semiconductor package, the method including: forming a release layer on a first carrier substrate, wherein the release layer includes a first portion and a second portion, wherein the first portion has a first thickness, and the second portion has a second thickness thicker than the first thickness; forming a barrier layer on the release layer; forming a redistribution layer on the barrier layer, wherein the redistribution layer includes wirings and an insulating layer; mounting a semiconductor chip on the redistribution layer; forming a molding layer on the redistribution layer to at least partially surround the semiconductor chip; attaching a second carrier substrate onto the molding layer; removing the first carrier substrate and the release layer; removing the barrier layer; and attaching a solder ball onto the redistribution layer exposed by removal of the barrier layer and the second portion of the release layer.

First claim

What is claimed is:

1. A semiconductor package comprising:
a redistribution layer including an electrode pad, an electrode pad support layer surrounding the electrode pad, a first wiring in contact with the electrode pad, and a first insulating layer surrounding the first wiring,
a semiconductor chip on an upper surface of the redistribution layer; and
a solder ball in contact with the electrode pad and protruding from a lower surface of the redistribution layer,
wherein a first height from the lower surface of the redistribution layer to the electrode pad is less than the a second height from the lower surface of the redistribution layer to the first wiring, and
a width of the electrode pad increases from the lower surface of the redistribution layer toward the upper surface of the redistribution layer.

2. The semiconductor package of claim 1 , wherein at least of the solder ball is in contact with the electrode pad supporter layer.

3. The semiconductor package of claim 1 , wherein the lower surface of the redistribution layer and a lower surface of the electrode pad support layer are coplanar.

4. The semiconductor package of claim 1 , wherein the redistribution layer further includes a via on the first wiring, a second insulating layer surrounding the via, a second wiring on the via, and a third insulating layer surrounding the via.

5. The semiconductor package of claim 4 , a width of the via increases from the lower surface of the redistribution layer toward the upper surface of the redistribution layer.

6. The semiconductor package of claim 1 , the width of the electrode pad in contact with the solder ball is different from a width of the solder ball in contact with the electrode pad.

7. The semiconductor package of claim 1 , wherein the electrode pad support layer includes a same material as the first insulating layer.

8. The semiconductor package of claim 7 , wherein the material includes photosensitive insulating material.

9. The semiconductor package of claim 1 , wherein the electrode pad includes a same material as the first wiring.

10. The semiconductor package of claim 1 , wherein further comprising a molding layer covering at least of the semiconductor chip on the upper surface of the redistribution layer.

11. The semiconductor package of claim 1 , wherein further comprising a connection terminal connecting the semiconductor chip and the redistribution layer.

12. A semiconductor package comprising:
an electrode pad support layer;
an electrode pad in the electrode pad support layer, a lower surface of the electrode pad is disposed above a lower surface of the electrode pad support layer;
a first insulating layer on the electrode pad support layer;
a first wiring being in contact with the electrode pad in the first insulating layer;
a semiconductor chip mounted on the first wiring; and
a solder ball being in contact with the electrode pad in the electrode pad support layer,
wherein a width of the first wiring is greater than a width of the electrode pad.

13. The semiconductor package of claim 11 , wherein the width of the electrode pad increases from a lower surface of the electrode pad support layer toward an upper surface of the electrode pad support layer.

14. The semiconductor package of claim 11 , wherein the electrode pad support layer includes a same material as the first insulating layer.

15. The semiconductor package of claim 11 , the width of the electrode pad in contact with the solder ball is different from a width of the solder ball in contact with the electrode pad.

16. The semiconductor package of claim 11 , wherein the electrode pad support layer includes a same material as the first insulating layer.

17. A semiconductor package comprising:
a redistribution layer including an electrode pad, an electrode pad support layer surrounding the electrode pad, a plurality of insulating layers on the electrode pad support layer, a plurality of wirings stacked sequentially inside the plurality of insulating layers, and a plurality of vias which penetrate the insulating layers and connect the wirings to each other and the electrode pad and the wirings to each other, the redistribution layer including a first surface and a second surface opposite to each other,
a trench exposing at least of the electrode pad and at least of the electrode pad support layer in the redistribution layer,
a solder ball connected the electrode pad in the trench;
a first semiconductor chip mounted on the first surface of the redistribution layer;
a first molding layer covering at least of the first semiconductor chip on the first surface of the redistribution layer; and
a width of the electrode pad and a width of the vias increase from the second surface of the redistribution layer toward the first surface of the redistribution layer.

18. The semiconductor package of claim 17 , further comprising:
a second semiconductor chip mounted on the first semiconductor chip,
a second molding layer covering at least of the first semiconductor chip on the first molding layer,
a penetration via penetrating the first molding layer, and
a connection terminal connecting the semiconductor chip and the penetration via.

19. The semiconductor package of claim 17 , further comprising:
a substrate on the first semiconductor chip,
a second semiconductor chip mounted on the substrate,
a penetration via penetrating the first molding layer, and
a connection terminal connecting the substrate and the penetration via.

20. The semiconductor package of claim 17 , further comprising:
a base layer on the first surface of the redistribution layer,
a plurality of sub pads in the base layer,
a plurality of sub via penetrating the base layer and connecting the sub pads to each other,
a substrate on the first semiconductor chip,
a second semiconductor chip mounted on the substrate, and
a connection terminal connecting the substrate and the sub via.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Park Jung-Ho
• Park Jin-Woo
• Lee Seok Hyun
• Jang Jae Gwon
• Jeon Gwang Jae

Classifications

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W74/15

  on active surfaces of flip-chip devices, e.g. underfills · CPC title

• H10W90/00

  Package configurations · CPC title

• H10W70/60

  Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) · CPC title