Method of forming package structure

Patent metadata

Field	Value
Publication number	US-2019172818-A1
Application number	US-201916272973-A
Country	US
Kind code	A1
Filing date	Feb 11, 2019
Priority date	Nov 28, 2016
Publication date	Jun 6, 2019
Grant date	—

Abstract

A method includes forming an under bump metallization (UBM) layer over a dielectric layer, forming a redistribution structure over the UBM layer, disposing a semiconductor device over the redistribution structure, removing a portion of the dielectric layer to form an opening to expose the UBM layer, and forming a conductive bump in the opening such that the conductive bump is coupled to the UBM layer.

First claim

What is claimed is:

1 . A method, comprising:
forming an under bump metallization (UBM) layer over a dielectric layer; forming a redistribution structure over the UBM layer; disposing a semiconductor device over the redistribution structure; removing a portion of the dielectric layer to form an opening to expose the UBM layer; and forming a conductive bump in the opening such that the conductive bump is coupled to the UBM layer.

2 . The method of claim 1 , wherein the opening is defined by an opening-defining wall of the dielectric layer buffer layer; and wherein forming the conductive bump is performed such that the conductive bump is in contact with the opening-defining wall of the dielectric layer.

3 . The method of claim 1 , wherein removing the portion of the dielectric layer comprises laser drilling the dielectric layer.

4 . The method of claim 1 , further comprising:
forming a conductive feature over the redistribution structure, wherein disposing the semiconductor device is performed such that the semiconductor device is coupled to the conductive feature.

5 . The method of claim 4 , further comprising forming a molding compound that surrounds the conductive feature and the semiconductor device.

6 . The method of claim 5 , wherein forming the molding compound is performed such that a top surface of the molding compound is substantially coplanar with a top surface of the conductive feature.

7 . The method of claim 4 , further comprising testing the conductive feature prior to disposing the semiconductor device over the redistribution structure.

8 . The method of claim 1 , wherein testing the redistribution structure prior to disposing the semiconductor device over the redistribution structure.

9 . The method of claim 1 , further comprising performing an electrical test on the semiconductor device after disposing the semiconductor device over the redistribution structure.

10 . The method of claim 9 , further comprising removing the semiconductor device if the electrical test identifies the semiconductor device is a bad die.

11 . A method, comprising:
forming a second dielectric layer over a first dielectric layer; patterning the second dielectric layer to form a protrusion over the first dielectric layer; forming a under bump metallization (UBM) layer conformally over the protrusion; disposing a semiconductor device over the UBM layer; and removing a portion of the first dielectric layer and the protrusion to expose the UBM layer.

12 . The method of claim 11 , wherein forming the UBM layer comprises:
forming a seed layer over the protrusion; forming a conductive feature over the seed layer; and removing the seed layer not covered by the conductive feature.

13 . The method of claim 11 , further comprising:
forming a seed layer in contact with the UBM layer; forming a conductive feature over the seed layer; and removing the seed layer not covered by the conductive feature.

14 . The method of claim 13 , further comprising:
forming a third dielectric layer over the UBM layer; forming an opening in the third dielectric layer to expose the UBM layer, wherein the opening tapers toward the UBM layer; and wherein forming the seed layer and forming the conductive feature are performed such that the seed layer and the conductive feature extend into the opening.

15 . The method of claim 11 , wherein patterning the second dielectric layer is performed such that the protrusion tapers away from the first dielectric layer.

16 . A method, comprising:
forming a redistribution structure over a carrier; performing a first electrical test on the redistribution structure; disposing a semiconductor device over the redistribution structure after performing the first electrical test; and molding the semiconductor device with a molding compound.

17 . The method of claim 16 , further comprising:
performing a second electrical test after disposing the semiconductor device over the redistribution structure.

18 . The method of claim 17 , further comprising:
replacing the semiconductor device with another semiconductor device if the second electrical test identifies the semiconductor device is a bad die.

19 . The method of claim 16 , further comprising forming a conductive feature over the redistribution structure, wherein molding the semiconductor device is performed such that the conductive feature is surrounded by the molding compound.

20 . The method of claim 19 , wherein the first electrical test is performed on the conductive feature.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Lin Jing-Cheng
• Tsai Po-Hao

Classifications

• H10W74/142

  the encapsulations exposing the passive side of the semiconductor body · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W72/0198

  batch processes · CPC title

• H10W70/60

  Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) · CPC title

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title