Eliminate sawing-induced peeling through forming trenches

Patent metadata

Field	Value
Publication number	US-10157854-B2
Application number	US-201815939595-A
Country	US
Kind code	B2
Filing date	Mar 29, 2018
Priority date	Mar 16, 2015
Publication date	Dec 18, 2018
Grant date	Dec 18, 2018

Abstract

A package includes a device die, a molding material encircling the device die, wherein a top surface of the molding material is substantially level with a top surface of the device die, and a bottom dielectric layer over the device die and the molding material. A plurality of redistribution lines (RDLs) extends into the bottom dielectric layer and electrically coupling to the device die. A top polymer layer is over the bottom dielectric layer, with a trench ring penetrating through the top polymer layer. The trench ring is adjacent to edges of the package. The package further includes Under-Bump Metallurgies (UBMs) extending into the top polymer layer.

First claim

What is claimed is:

1. A method comprising:
encapsulating a first device die and a second device die in an encapsulating material;
forming a first dielectric layer over and contacting the first device die, the second device die, and the encapsulating material;
performing a light exposure on the first dielectric layer using a lithography mask;
developing the first dielectric layer that is light-exposed to simultaneously forming a first opening overlapping the first device die, a second opening overlapping the second device die, and a trench overlying a scribe line portion of the encapsulating material between the first device die and the second device die; and
sawing the encapsulating material, wherein a kerf of the sawing passes through the trench.

2. The method of claim 1 , wherein after the sawing, the first opening and the second opening are separated into a first package and a second package, respectively.

3. The method of claim 2 , wherein the trench is separated by the sawing into a first portion in the first package and a second portion in the second package.

4. The method of claim 1 further comprising:
forming a second dielectric layer comprising a first portion over and contacting the first dielectric layer, and a second portion in the trench;
patterning the second dielectric layer to form an additional trench in the second dielectric layer; and
forming a third dielectric layer over and contacting the second dielectric layer, wherein the third dielectric layer extends into the additional trench.

5. The method of claim 4 , wherein the additional trench forms a trench ring encircling a region directly over the first device die.

6. The method of claim 4 further comprising patterning the third dielectric layer, wherein in the patterning the third dielectric layer, a portion of the third dielectric layer extending into the additional trench is removed.

7. The method of claim 1 , wherein after the first dielectric layer is developed, a portion of the first dielectric layer remains under the trench.

8. A method comprising:
encapsulating a device die in an encapsulating material;
forming a first dielectric layer over and contacting the device die and the encapsulating material;
simultaneously forming first openings and a trench in the first dielectric layer, wherein conductive features of the device die are exposed through the first openings;
forming first Redistribution Lines (RDLs) to fill the first openings; and
forming a second dielectric layer over the first RDLs, wherein the second dielectric layer fully fills the trench.

9. The method of claim 8 further comprising:
patterning the second dielectric layer to form:
a first trench ring penetrating through the second dielectric layer; and
second openings encircled by the first trench ring, wherein a top surface of the first dielectric layer is exposed to the first trench ring, and top surfaces of the RDLs are exposed to the second openings.

10. The method of claim 9 further comprising:
forming second RDLs to fill the second openings; and
forming a third dielectric layer having a first portion over the second RDLs and a second portion extending into the first trench ring; and
patterning the third dielectric layer to form a second trench ring.

11. The method of claim 10 , wherein in a top view of the device die, a first one of the first trench ring and the second trench ring encircles a second one of the first trench ring and the second trench ring.

12. The method of claim 10 , wherein the second trench ring overlaps the first trench ring, and a top surface of the first dielectric layer is exposed to the second trench ring.

13. The method of claim 10 , wherein the second trench ring overlaps the first trench ring, and after the second dielectric layer is patterned, a portion of the second dielectric layer remains in the first trench ring.

14. The method of claim 9 further comprising sawing through the first dielectric layer, the second dielectric layer, and the encapsulating material to form a package, wherein a kerf of the sawing passes through the trench.

15. A method comprising:
encapsulating a first device die in an encapsulating material;
forming a first dielectric layer over and contacting the first device die and the encapsulating material;
simultaneously forming openings and a trench in the first dielectric layer, wherein conductive features of the first device die are exposed through the openings, and the encapsulating material is exposed through the trench; and
forming Redistribution Lines (RDLs) to fill the openings, wherein after the RDLs are formed, the encapsulating material is exposed through the trench.

16. The method of claim 15 , wherein the encapsulating material further encapsulates a second device die therein, and the trench overlaps a scribe line between the first device die and the second device die.

17. The method of claim 15 further comprising:
forming a second dielectric layer having a first portion over and contacting the first dielectric layer, and a second portion extending into the trench; and
patterning the second dielectric layer to at least partially remove the second portion of the second dielectric layer.

18. The method of claim 17 , wherein after the second dielectric layer is patterned, the encapsulating material is exposed through the trench.

19. The method of claim 17 , wherein after the second dielectric layer is patterned, the second portion of the second dielectric layer has a remaining portion in the trench.

20. The method of claim 15 further comprising sawing through the trench.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chen Jie
• Chen Hsien-Wei

Classifications

• H10W90/722

  between stacked chips · CPC title

• H10W90/28

  the stacked chips having different sizes, e.g. chip stacks having a pyramidal shape · CPC title

• H10W72/0198

  batch processes · CPC title

• H10W70/099

  Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers · CPC title

• H10W72/884

  Die-attach connectors and bond wires · CPC title