Stacked-die MEMS resonator

Patent metadata

Field	Value
Publication number	US-11708264-B2
Application number	US-202217827437-A
Country	US
Kind code	B2
Filing date	May 27, 2022
Priority date	Jun 15, 2006
Publication date	Jul 25, 2023
Grant date	Jul 25, 2023

Abstract

A low-profile packaging structure for a microelectromechanical-system (MEMS) resonator system includes an electrical lead having internal and external electrical contact surfaces at respective first and second heights within a cross-sectional profile of the packaging structure and a die-mounting surface at an intermediate height between the first and second heights. A resonator-control chip is mounted to the die-mounting surface of the electrical lead such that at least a portion of the resonator-control chip is disposed between the first and second heights and wire-bonded to the internal electrical contact surface of the electrical lead. A MEMS resonator chip is mounted to the resonator-control chip in a stacked die configuration and the MEMS resonator chip, resonator-control chip and internal electrical contact and die-mounting surfaces of the electrical lead are enclosed within a package enclosure that exposes the external electrical contact surface of the electrical lead at an external surface of the packaging structure.

First claim

What is claimed is:

1. An integrated circuit comprising:
a first die having a microelectromechanical system (MEMS) resonator;
a second die having complementary metal oxide semiconductor (CMOS) circuitry;
wherein the first die and the second die are stacked together and are directly electrically interconnected by at least one of wire bonds or solder bumps;
one or more metallic structures on an exterior surface of the integrated circuit, the one or more metaling structures being in electrical communication with the CMOS circuitry;
encapsulation of the first die and the at least one of the wirebonds or solder bumps, relative to the second die, that seals the first die from an atmosphere external to the integrated circuit;
wherein the one or more metallic structures are to electrically connect the integrated circuit with external electronics.

2. The integrated circuit of claim 1 wherein:
the integrated circuit comprises a lead frame, the lead frame to couple the second die to the one or more metallic structures; and
encapsulation seals each of the first die and the second die, relative to the lead frame, from the atmosphere external to the integrated circuit.

3. The integrated circuit of claim 1 wherein:
the integrated circuit comprises a paddle, the paddle to couple the second die to the one or more metallic structures; and
encapsulation encapsulates each of the first die and the second die, relative to the paddle.

4. The integrated circuit of claim 3 wherein the second die is attached to the paddle by an electrically conductive epoxy.

5. The integrated circuit of claim 1 wherein:
at least one of the first die and the second die comprises a passivation layer;
the passivation layer is characterized by apertures therethrough; and
the integrated circuit comprises a thermally-conductive material within the apertures, the thermally conductive material adhering the first die with the second die and providing for thermal communication between the MEMS resonator and a temperature sensor on the second die.

6. The integrated circuit of claim 1 wherein the first die and the second die are interconnected to each other by an epoxy having a coefficient of thermal expansion between two-millionths and one-hundred and seventy millionths per degree Centigrade.

7. The integrated circuit of claim 1 wherein the integrated circuit has a footprint of less than 1.6 millimeters by 2.0 millimeters.

8. A method of fabricating an integrated circuit, the method comprising:
providing a first die having a microelectromechanical system (MEMS) resonator and a second die having complementary metal oxide semiconductor (CMOS) circuitry;
stacking the first die and the second die together, in a manner directly electrically interconnected by at least one of wire bonds or solder bumps;
electrically coupling the CMOS circuitry of the second die with one or more metallic structures; and
encapsulating the first die and the at least one of the wirebonds or solder bumps, relative to the second die, so as to seal the first die from an atmosphere external to the integrated circuit;
wherein the one or more metallic structures are to electrically connect the integrated circuit with external electronics.

9. The method of claim 8 wherein the method further comprises, after the encapsulating, singulating the integrated circuit.

10. The method of claim 8 wherein:
the method further comprises electrically coupling the second die to a lead frame, the lead frame to electrically couple the second die to the one or more metallic structures; and
the method further comprises encapsulating each of the first die and the second die, relative to the lead frame.

11. The method of claim 8 wherein:
the method further comprises electrically coupling the second die to a paddle, the paddle bearing the one or more metallic structures, paddle to electrically couple the second die to the one or more metallic structures; and
the method further comprises encapsulating each of the first die and the second die, relative to the paddle.

12. The method of claim 11 further comprising attaching the second die to the paddle by an electrically conductive epoxy.

13. The method of claim 8 wherein:
at least one of the first die and the second die comprises a passivation layer;
the method further comprises forming apertures through the passivation layer and depositing a thermally-conductive material within the apertures, and adhering the first die with the second die using the thermally-conductive material so as to provide thermal communication between the MEMS resonator and a temperature sensor on the second die.

14. The method of claim 8 further comprising interconnecting the first die and the second die to each other using an epoxy having a coefficient of thermal expansion between two-millionths and one-hundred and seventy millionths per degree Centigrade.

15. The method of claim 8 further comprising forming the integrated circuit to have a footprint of less than 1.6 millimeters by 2.0 millimeters.

16. A method of fabricating an oscillator integrated circuit, the method comprising:
providing a first die having a MEMS resonator and a second die having complementary metal oxide semiconductor (CMOS) circuitry, wherein the second die is to generate an oscillation signal for output by the oscillator integrated circuit to external electronics in dependence on vibration of the MEMS resonator;
stacking the first die and the second die together in a manner such that they are directly electrically interconnected by solder bumps;
electrically coupling the CMOS circuitry of the second die with one or more metallic structures that are to be on an exterior surface of the integrated circuits, the one or more metallic structures to output the oscillation signal;
encapsulating the first die and the at least one of the wirebonds or solder bumps, relative to the second die, so as to seal the first die relative to an atmosphere external to the oscillator integrated circuit; and
singulating the oscillator integrated circuit.

17. The method of claim 16 wherein:
the method further comprises electrically coupling the second die to a lead frame, the lead frame to electrically couple the second die to the one or more metallic structures; and
the method further comprises encapsulating each of the first die and the second die, relative to the lead frame.

18. The method of claim 16 wherein:
the method further comprises electrically coupling the second die to a paddle, the paddle bearing the one or more metallic structures, paddle to electrically couple the second die to the one or more metallic structures; and
the method further comprises encapsulating each of the first die and the second die, relative to the paddle.

19. The method of claim 18 further comprising attaching the second die to the paddle by an electrically conductive epoxy.

20. The method of claim 18 wherein singulating the oscillator integrated circuit further comprises forming the integrated circuit to have a footprint of less than 1.6 millimeters by 2.0 millimeters.

Assignees

• Sitime Corp

Inventors

• Gupta Pavan
• Partridge Aaron
• Lutz Markus

Classifications

• H10W90/756

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W74/111

  the semiconductor body being completely enclosed · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W72/884

  Die-attach connectors and bond wires · CPC title

• H10W70/60

  Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) · CPC title