Manufacturing of integrated circuit resonator

US10913655B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10913655-B2
Application numberUS-202016903116-A
CountryUS
Kind codeB2
Filing dateJun 16, 2020
Priority dateJun 15, 2006
Publication dateFeb 9, 2021
Grant dateFeb 9, 2021

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A low-profile packaging structure for a microelectromechanical-system (MEMS) resonator system includes an electrical lead having internal and external electrical contact surfaces at respective first and second heights within a cross-sectional profile of the packaging structure and a die-mounting surface at an intermediate height between the first and second heights. A resonator-control chip is mounted to the die-mounting surface of the electrical lead such that at least a portion of the resonator-control chip is disposed between the first and second heights and wire-bonded to the internal electrical contact surface of the electrical lead. A MEMS resonator chip is mounted to the resonator-control chip in a stacked die configuration and the MEMS resonator chip, resonator-control chip and internal electrical contact and die-mounting surfaces of the electrical lead are enclosed within a package enclosure that exposes the external electrical contact surface of the electrical lead at an external surface of the packaging structure.

First claim

Opening claim text (preview).

What is claimed is: 1. A method of manufacturing an integrated circuit resonator, the method comprising: mounting a device chip having a resonator to a control chip in a manner that places a surface of the device chip in thermal conductance with a surface of the control chip, the control chip having a temperature sensor; electrically coupling electrical contacts of the device chip with electrical contacts of the control chip, in a manner that provides for, during operation of the integrated circuit resonator, electrical communication of a signal from the device chip to the control chip representing a sensed frequency of the resonator; and providing for one or more electrical connections that are to, during operation of the integrated circuit resonator, output a temperature-corrected timing signal from the control chip. 2. The method of claim 1 , wherein: mounting comprises applying a thermally-conductive epoxy to one of the surface of the device chip and the surface of the resonator chip, and stacking the surface of the device chip with the surface of the resonator chip, with the conductive epoxy therebetween. 3. The method of claim 2 , wherein the thermally-conductive epoxy has a coefficient of thermal expansion that is matched to a coefficient of thermal expansion for crystal silicon. 4. The method of claim 2 , wherein the thermally-conductive epoxy has a coefficient of thermal expansion that is between 0.000002 per degree Celsius and 0.000017 per degree Celsius. 5. The method of claim 2 , wherein the thermally-conductive epoxy is also electrically-conductive. 6. The method of claim 1 , wherein electrically coupling comprises wirebonding the electrical contacts of the control chip with the electrical contacts of the device chip. 7. The method of claim 1 , wherein electrically coupling comprises forming solder bumps on at least one of the electrical contacts of the control chip and the electrical contacts of the electrical chip and wherein the method further comprises mounting the device chip to the control chip using a flip-chip process in which the electrical contacts of the control chip are aligned with respective ones of the electrical contacts of the device chip and in which the solder bumps are reflowed. 8. The method of claim 1 , wherein: the method further comprises mounting at least one of the device chip and the control chip to a package support structure; and providing the one or more electrical connections further comprises electrically coupling an output electrical contact of the control chip with an output electrical contact of the package support structure. 9. The method of claim 8 , wherein: the package support structure comprises a lead frame; and providing the one or more electrical connections comprises wirebonding the output electrical contact of the control chip with the output electrical contact of the package support structure. 10. The method of claim 8 , wherein: the package support structure comprises an adhesive tape; and providing the one or more electrical connections comprises electrically coupling the output electrical contact of the control chip with an electrical layer of the adhesive tape. 11. The method of claim 10 , wherein: mounting further comprises enclosing the device chip and the control chip against the adhesive tape using a mold compound. 12. The method of claim 8 , wherein: the package support structure comprises a lead frame; and providing the one or more electrical connections comprises forming a solder bump on at least one of the output electrical contact of the control chip and a metal layer of the lead frame, and reflowing the solder bump. 13. The method of claim 1 , further comprising dicing the integrated circuit resonator from a wafer having multiple resonator structures. 14. The method of claim 1 , wherein the resonator comprises a microelectromechanical systems (MEMS) resonator. 15. The method of claim 1 , wherein the resonator comprises a nanoelectromechanical systems (NEMS) resonator. 16. A method of manufacturing an integrated circuit resonator, the method comprising: forming a die stack, comprising mounting a device chip having a resonator to a control chip in a manner that places a surface of the device chip in thermal conductance with a surface of the control chip, the control chip having a temperature sensor, and electrically coupling electrical contacts of the device chip with electrical contacts of the control chip, in a manner that provides for, during operation of the integrated circuit resonator, electrical communication of a signal from the device chip to the control chip representing a sensed frequency of the resonator; and providing for a package support structure that mounts the die stack, the package support structure having an output electrical contact in electrical communication with the control chip so as to output a temperature-corrected timing signal from the control chip. 17. The method of claim 16 , wherein: mounting comprises applying a thermally-conductive epoxy to one of the surface of the device chip and the surface of the resonator chip, and stacking the surface of the device chip with the surface of the resonator chip, with the conductive epoxy therebetween. 18. The method of claim 17 , wherein the thermally-conductive epoxy has a coefficient of thermal expansion that is matched to a coefficient of thermal expansion of crystal silicon. 19. The method of claim 17 , wherein the thermally-conductive epoxy has a coefficient of thermal expansion that is between 0.000002 per degree Celsius and 0.000017 per degree Celsius. 20. The method of claim 16 , wherein electrically coupling comprises wirebonding the electrical contacts of the control chip with the electrical contacts of the device chip. 21. The method of claim 16 , wherein electrically coupling comprises forming solder bumps on at least one of the electrical contacts of the control chip and the electrical contacts of the electrical chip and wherein the method further comprises mounting the device chip to the control chip using a flip-chip process in which the electrical contacts of the control chip are aligned with respective ones of the electrical contacts of the device chip and in which the solder bumps are reflowed. 22. The method of claim 16 , wherein: the package support structure comprises a lead frame; and the method further comprises wirebonding the output electrical contact of the control chip with the output electrical contact of the package support structure. 23. The method of claim 16 , wherein: the package support structure comprises an adhesive tape; and the method further comprises electrically connecting the output electrical contact of the control chip with an electrical layer of the adhesive tape. 24. The method of claim 23 , wherein: providing for the package support structure comprises enclosing the device chip and the control chip against the adhesive tape using a mold compound. 25. The method of claim 16 , wherein: the package support structure comprises a lead frame; and providing for the package support structure comprises forming a solder bump on at least one of the output electrical contact of the control chip and a metal layer of the lead frame, and reflowing the solder bump. 26. The method of claim 16 , further comprising dicing the die stack from a wafer having multiple resonator structures.

Assignees

Inventors

Classifications

  • between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

  • the semiconductor body being completely enclosed · CPC title

  • Encapsulations, e.g. protective coatings · CPC title

  • Die-attach connectors and bond wires · CPC title

  • Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) · CPC title

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What does patent US10913655B2 cover?
A low-profile packaging structure for a microelectromechanical-system (MEMS) resonator system includes an electrical lead having internal and external electrical contact surfaces at respective first and second heights within a cross-sectional profile of the packaging structure and a die-mounting surface at an intermediate height between the first and second heights. A resonator-control chip is …
Who is the assignee on this patent?
Sitime Corp
What technology area does this patent fall under?
Primary CPC classification B81C1/0023. Mapped technology areas include Operations & Transport.
When was this patent published?
Publication date Tue Feb 09 2021 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 2 related publications on this page (citations in our corpus or others sharing the same primary CPC).