Prepare for shorter precision (round for reround) mode in a decimal floating-point instruction

Patent metadata

Field	Value
Publication number	US-11698772-B2
Application number	US-202017026407-A
Country	US
Kind code	B2
Filing date	Sep 21, 2020
Priority date	Mar 1, 2007
Publication date	Jul 11, 2023
Grant date	Jul 11, 2023

Abstract

An instruction is executed in round-for-reround mode wherein the permissible resultant value that is closest to and no greater in magnitude than the infinitely precise result is selected. If the selected value is not exact and the units digit of the selected value is either 0 or 5, then the digit is incremented by one and the selected value is delivered. In all other cases, the selected value is delivered.

First claim

What is claimed is:

1. A computer implemented method for indicating with any least significant decimal coefficient digit of 0 or 5 that a result of a rounding of a decimal floating-point (DFP) number to a lesser precision in a computer processor is an exact (precise) result, the method comprising:
fetching a DFP round-for-reround instruction in a machine, the machine implementing a plurality of floating point registers and including the computer processor:
executing, by the computer processor, the DFP round-for-reround instruction in a round-for-reround mode, wherein the DFP round-for-reround instruction is configured to perform a DFP operation on a DFP operand, the executing the DFP round-for-reround instruction comprising:
based on being in the round-for-reround mode, forming, by the computer processor, from a decimal coefficient number having a high order portion and a low order portion, an intermediate result from the high order portion, wherein the intermediate result has a least significant decimal coefficient digit;
without changing any coefficient digit of the intermediate result, other than the least significant decimal coefficient digit, creating from the intermediate result a rounded-for-reround DFP number, the creating comprising:
based on the least significant coefficient digit of the intermediate result being 0 or 5 and based on the low order portion having any value other than 0, incrementing the least significant coefficient digit of the intermediate result; and
storing in computer processor storage, by the computer processor, the intermediate result as a final result of the executed DFP operation, wherein the intermediate result is the rounded-for-reround DFP number, wherein a final result having a least significant digit of 0 or 5 indicates that the final result is exact and that the low order portion is 0, wherein a final result having a least significant digit of any one of 1, 2, 3, 4, 6, 7, 8 and 9 does not indicate that the final result is exact and does not indicate that the low order portion is 0.

2. The computer implemented method according to claim 1 , the creating further comprising:
based on the least significant coefficient digit of the intermediate result being 0 or 5 and based on the low order portion having a most significant decimal digit of less than 5, incrementing the least significant digit of the intermediate result.

3. The computer implemented method according to claim 1 , further comprising:
subsequent to executing the DFP round-for-reround instruction, executing, by the computer processor, a DFP reround instruction, the executing comprising:
rounding, by the computer processor, the rounded-for-reround DFP number to produce a rounded result, the rounded result represents a DFP number having at least 1 fewer decimal coefficient digits of precision than the second number of decimal coefficient digits of precision; and
storing in computer processor storage, by the computer processor, the rounded result as a result of the execution of the DFP reround instruction.

4. The computer implemented method according to claim 1 , the executing further comprising determining the round-for-reround mode is enabled based on any one of a round-for-reround value of a first rounding field of a Floating Point Control (FPC) register and a round-for-reround value of a second rounding field of the round-for-reround instruction.

5. The computer implemented method according to claim 4 , the determining that the round-for-reround mode is enabled further comprising using the second rounding field of the round-for-reround instruction to select whether to use the first rounding field or the second rounding field to determine that the round-for-reround mode is enabled.

6. The computer implemented method according to claim 1 , further comprising:
executing, by the computer processor, another instance of the DFP round-for-reround instruction in the round-for-reround mode, wherein the other instance of the DFP round-for-reround instruction is configured to perform another DFP operation on another DFP operand, the executing the other instance of the DFP round-for-reround instruction comprising:
forming, by the computer processor, from another decimal coefficient number having another high order portion and another low order portion, another intermediate result from the high order portion, wherein the other intermediate result has another least significant decimal coefficient digit;
without changing any coefficient digit of the other intermediate result, other than the other least significant decimal coefficient digit, creating from the other intermediate result another rounded-for-reround DFP number, the creating comprising:
based on the other low order portion being 0, leaving the other least significant coefficient digit of the other intermediate result unchanged; and
storing in computer processor storage, by the computer processor, the other intermediate result as another final result of the executed other DFP operation, wherein the other intermediate result is the other rounded-for-reround DFP number, wherein a final result having a least significant digit of 0 or 5 indicates that the final result is exact and that the low order portion is 0, wherein a final result having a least significant digit of any one of 1, 2, 3, 4, 6, 7, 8 and 9 does not indicate that the final result is exact and does not indicate that the low order portion is 0.

7. The computer implemented method according to claim 1 , the creating further comprising:
based on the least significant coefficient digit of the intermediate result being 0 or 5 and based on the low order portion having a most significant decimal digit of greater than 5, incrementing the least significant digit of the intermediate result.

8. The computer-implemented method according to claim 1 , wherein the creating further comprises:
based on the least significant coefficient digit of the intermediate result being 0 and based on the low order portion having any value other than 0, incrementing the least significant coefficient digit of the intermediate result; and
based on the least significant coefficient digit of the intermediate result being 5 and based on the low order portion having any value other than 0, incrementing the least significant coefficient digit of the intermediate result.

9. The computer-implemented method according to claim 1 , wherein the DFP operand is fetched by an execution unit of the computer processor.

10. A computer system for indicating with any least significant decimal coefficient digit of 0 or 5 that a result of a rounding of a decimal floating-point (DFP) number to a lesser precision in a computer processor is an exact (precise) result, the computer system comprising:
an instruction fetching unit for fetching instructions to be executed;
a floating point arithmetic unit for executing floating point operations for executing fetched floating point instructions; and
an operand storage in communication with said floating point arithmetic unit; and
a memory communicatively coupled to said computer processor, the computer system configured to perform a method comprising:
executing, by the computer processor, a DFP round-for-reround instruction in a round-for-reround mode, wherein the DFP round-for-reround instruction is configured to perform a DFP operation on a DFP operand, the executing the DFP round-for-reround instruction comprising:
based on being in the round-for-reround mode, forming, by the computer processor, from a decimal coefficient number having a high order portion and a low order portion, an intermediate result from the high order portion, wherein the intermediate result has a least significant decimal coeffi

Assignees

• IBM

Inventors

• Schwarz Eric Mark
• Schmookler Martin Stanley

Classifications

• G06F7/49947

  Rounding · CPC title

• H05K999/00

  Electricity · mapped topic

• G06F7/49973

  Rounding towards negative infinity, e.g. truncation of two's complement numbers (G06F7/49957 takes precedence) · CPC title

• G06F7/386

  decimal, radix 20 or 12 (G06F7/385 takes precedence) · CPC title

• G06F7/49968

  Rounding towards positive infinity (G06F7/49957 takes precedence) · CPC title