Load-hit-load detection in an out-of-order processor

Patent metadata

Field	Value
Publication number	US-10534616-B2
Application number	US-201715726563-A
Country	US
Kind code	B2
Filing date	Oct 6, 2017
Priority date	Oct 6, 2017
Publication date	Jan 14, 2020
Grant date	Jan 14, 2020

Abstract

Technical solutions are described for executing one or more out-of-order instructions by a load-store unit (LSU) by detecting a load-hit-load (LHL) case based only on effective addresses (EA). An example method includes, in response to receiving a first load instruction, creating an entry in a LHL table. Further, in response to receiving a second load instruction in the load reorder queue, and in response to the predetermined number of bits from a second EA used by the second load instruction matching the predetermined number of bits from the first EA, comparing the first EA and the second EA. Further, a first thread identifier for the first load instruction is compared with a second thread identifier for the second load instruction. In response to the first EA matching the second EA, and the first thread identifier matching the second thread identifier, the method includes flushing the first load instruction.

First claim

What is claimed is:

1. A processing unit for executing one or more instructions, the processing unit comprising:
a load-store unit for transferring data between memory and registers, the load-store unit configured to detect and flush a load-hit-load (LHL) when executing a set of instruction in an out of order (OoO) window, the detecting and flushing comprising:
in response to receiving a first load instruction in a load reorder queue, creating an entry in a LHL table, the entry storing a predetermined number of bits from a first effective address used by the first load instruction;
in response to receiving a second load instruction in the load reorder queue, and in response to the predetermined number of bits from a second effective address used by the second load instruction matching the predetermined number of bits from the first effective address that are stored in the LHL table:
comparing the first effective address and the second effective address;
comparing a first thread identifier for the first load instruction and a second thread identifier for the second load instruction; and
in response to the first effective address matching the second effective address, and the first thread identifier matching the second thread identifier, flushing the first load instruction; and
in response to the first thread identifier and the second thread identifier not matching, creating an entry in the LHL table for the second load instruction.

2. The processing unit of claim 1 , wherein the first load instruction is issued by a first processing core and the second load instruction is issued by a second core using a cross invalidation request.

3. The processing unit of claim 1 , wherein the load-store unit removes the entry from the LHL table in response to the first load instruction being deallocated.

4. The processing unit of claim 1 , wherein in response to the predetermined number of bits from the second effective address not matching the predetermined number of bits from the first effective address, create an entry in the LHL table for the second load instruction.

5. The processing unit of claim 1 , wherein in response to the first effective address and the second effective address not matching, create an entry in the LHL table for the second load instruction.

6. The processing unit of claim 1 , wherein flushing the first load instruction further comprises flushing instructions starting from the first load instruction by:
sending a flush message to an instruction fetch unit, the message comprises an identifier of the first load instruction, wherein the flushing comprises relinquishing launch of instructions fetched by the instruction fetch unit starting from the first load instruction.

7. The processing unit of claim 1 , wherein the LHL table comprises a number of partitions, one partition for each load instruction issued concurrently by the load-store unit.

8. A computer-implemented method for executing one or more out-of-order instructions by a processing unit, the method comprising:
detecting and flushing, by a load-store unit, a load-hit-load (LHL) in an out-of-order execution of instructions based only on effective addresses, the detecting and flushing comprising:
in response to receiving a first load instruction in a load reorder queue, creating an entry in a LHL table, the entry storing a predetermined number of bits from a first effective address used by the first load instruction; and
in response to receiving a second load instruction in the load reorder queue, and in response to the predetermined number of bits from a second effective address used by the second load instruction matching the predetermined number of bits from the first effective address that are stored in the LHL table:
comparing the first effective address and the second effective address;
comparing a first thread identifier for the first load instruction and a second thread identifier for the second load instruction; and
in response to the first effective address matching the second effective address, and the first thread identifier matching the second thread identifier, flushing the first load instruction; and
in response to the first thread identifier and the second thread identifier not matching, creating an entry in the LHL table for the second load instruction.

9. The computer-implemented method of claim 8 , wherein the first load instruction is issued by a first processing core and the second load instruction is issued by a second core using a cross invalidation request.

10. The computer-implemented method of claim 8 , wherein in response to the predetermined number of bits from the second effective address not matching the predetermined number of bits from the first effective address, create an entry in the LHL table for the second load instruction.

11. The computer-implemented method of claim 8 , wherein flushing the first load instruction further comprises flushing instructions starting from the first load instruction by:
sending a flush message to an instruction fetch unit, the message comprises an identifier of the first load instruction, wherein the flushing comprises relinquishing launch of instructions fetched by the instruction fetch unit starting from the first load instruction.

12. The computer-implemented method of claim 8 , wherein the LHL table comprises a number of partitions, one partition for each load instruction issued concurrently by the load-store unit.

13. The computer-implemented method of claim 8 , wherein the out-of-order execution of instructions comprises executing a predetermined set of instruction in an out of order (OoO) window non-sequentially.

14. A computer program product comprising a computer readable storage medium having program instructions embodied therewith, the program instructions executable by a processor to cause the processor to perform operations comprising:
detecting and flushing, by a load-store unit, a load-hit-load (LHL) in an out-of-order execution of instructions based only on effective addresses by:
in response to receiving a first load instruction in a load reorder queue, creating an entry in a LHL table, the entry storing a predetermined number of bits from a first effective address used by the first load instruction; and
in response to receiving a second load instruction in the load reorder queue, and in response to the predetermined number of bits from a second effective address used by the second load instruction matching the predetermined number of bits from the first effective address that are stored in the LHL table:
comparing the first effective address and the second effective address;
comparing a first thread identifier for the first load instruction and a second thread identifier for the second load instruction;
in response to the first effective address matching the second effective address, and the first thread identifier matching the second thread identifier, flushing the first load instruction; and

in response to the first thread identifier and the second thread identifier not matching, creating an entry in the LHL table for the second load instruction.

15. The computer program product of claim 14 , wherein the first load instruction is issued by a first processing core and the second load instruction is issued by a second core using a cross invalidation request.

16. The computer program product of claim 14 , wherein in response to the predetermined number of bits from the second effective address not matching the predetermined number of bits from the first effective address, create an entry in the LHL table for the second load in

Assignees

• IBM

Inventors

• Gonzalez Christopher
• Lloyd Bryan
• Sinharoy Balaram

Classifications

• G06F9/4881 Primary

  Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues · CPC title

• G06F9/24

  Loading of the microprogram · CPC title

• G06F9/3838

  Dependency mechanisms, e.g. register scoreboarding · CPC title

• G06F9/3861

  Recovery, e.g. branch miss-prediction, exception handling (error detection or correction G06F11/00) · CPC title

• G06F9/445

  Program loading or initiating (bootstrapping G06F9/4401; security arrangements for program loading or initiating G06F21/57) · CPC title