Hybrid power stage and gate driver circuit

Patent metadata

Field	Value
Publication number	US-11677396-B2
Application number	US-202017123316-A
Country	US
Kind code	B2
Filing date	Dec 16, 2020
Priority date	Dec 16, 2020
Publication date	Jun 13, 2023
Grant date	Jun 13, 2023

Abstract

Hybrid power switching stages and driver circuits are disclosed. An example semiconductor power switching device comprises a high-side switch and a low-side switch connected in a half-bridge configuration, wherein the high-side switch comprises a GaN power transistor and the low-side switch comprises a Si MOSFET. The Si—GaN hybrid switching stage provides enhanced performance, e.g. reduced switching losses, in a cost-effective solution which takes advantage of characteristics of power switching devices comprising both GaN power transistors and Si MOSFETs. Also disclosed is a gate driver for the Si—GaN hybrid switching stage, and a semiconductor power switching stage comprising the gate driver and a Si—GaN hybrid power switching device having a half-bridge or full-bridge switching topology.

First claim

The invention claimed is:

1. A power semiconductor switching stage comprising:
a hybrid power semiconductor switching device comprising: a high-side switch and a low-side switch connected in series in a half-bridge configuration, wherein:
the high-side switch is a Gallium Nitride (GaN) semiconductor power switching device implemented with at least one transistor, wherein every transistor of the high-side switch is an enhancement-mode GaN power transistor having a source, a drain and a gate; and
the low-side switch is a Silicon (Si) semiconductor power switching device implemented with at least one transistor, wherein every transistor of the low-side switch is an enhancement-mode Si MOSFET having a source, a drain and a gate;
the drain of every GaN power transistor is connected to a DC bus, the source of every GaN power transistor is connected to a switch node, the drain of every Si MOSFET is connected to the switch node, and the source of every Si MOSFET is connected to a source bus;
a MOSFET half-bridge gate driver comprising a high-side driver and a low-side driver;
a gate drive output of the low-side driver being connected to the gate of every Si MOSFET through a first gate drive circuit comprising a gate resistor to provide a gate drive of a first voltage range for driving every Si MOSFET;
a gate drive output of the high-side driver being connected to the gate of every GaN power transistor through a second gate drive circuit comprising a gate resistor and a voltage level shift circuit to provide a gate drive of a second voltage range for driving every GaN power transistor.

2. The power semiconductor switching stage of claim 1 , wherein the low-side switch comprises a plurality of Si MOSFETs connected in parallel.

3. The power semiconductor switching stage of claim 1 , wherein the high-side switch comprises a plurality of GaN power transistors connected in parallel.

4. The power semiconductor switching stage of claim 1 wherein, for a supply voltage V DD , said first voltage range for driving every Si MOSFET is a range from 0V to V DD , and the second voltage range for driving every GaN power transistor is level shifted to provide a positive turn-on gate voltage and a negative turn-off gate voltage.

5. The power semiconductor switching stage of claim 4 , wherein the voltage level shift circuit comprises a capacitor in parallel with a resistor, connected in series between the gate resistor and the gate of every GaN power transistor, and a clamp circuit connected between the gate of every GaN power transistor and the source of every GaN power transistor for clamping the positive turn-on gate voltage and the negative turn-off gate voltage.

6. The power semiconductor switching stage of claim 5 , wherein the clamp circuit comprises a diode clamp.

7. The power semiconductor switching stage of claim 1 , which is part of a half-bridge or full-bridge power switching stage.

8. The power semiconductor switching stage of claim 1 , wherein every GaN power transistor is a GaN HEMT.

9. The power semiconductor switching stage of claim 1 , wherein said MOSFET half-bridge gate driver is integrated with a driver controller.

10. A gate driver for a hybrid power switching device comprising a high-side switch and a low-side switch connected in series in a half-bridge configuration, wherein: the high-side switch is a Gallium Nitride (GaN) semiconductor power switching device implemented with at least one transistor, wherein every transistor of the high-side switch is an enhancement mode GaN power transistor having a source, a drain and a gate; and the low-side switch is an enhancement-mode Silicon (Si) semiconductor power switching device implemented with at least one transistor, wherein every power transistor of the low-side switch is a Si MOSFET having a source, a drain and a gate; the drain of every GaN power transistor is connected to a DC bus, the source of every GaN power transistor is connected to a switch node, the drain of every Si MOSFET is connected to the switch node, and the source of every Si MOSFET is connected to a source bus; the gate driver comprising:
a half-bridge driver comprising a high-side driver and a low-side driver;
a gate drive output of the low-side driver being connected through a first gate drive circuit comprising a first gate resistor to provide a gate drive voltage output of a first voltage range for driving the gate of every Si MOSFET of the low-side switch;
a gate drive output of the high-side driver being connected through a second gate drive circuit comprising a gate resistor and a voltage level shift circuit to provide a gate drive voltage output of a second voltage range for driving the gate of every GaN transistor of the high-side switch.

11. The gate driver of claim 10 , wherein for a supply voltage V DD , the first voltage range for driving the Si semiconductor power switching device is in a range from 0V to V DD and the second voltage range for driving the GaN semiconductor power switching device is level shifted to provide a positive turn-on gate voltage and a negative turn-off gate voltage.

12. The gate driver of claim 11 , wherein the level shift circuit comprises a capacitor in parallel with a resistor, connected in series between the gate resistor and the gate of every GaN power transitor, and a clamp circuit connected between the gate of every GaN power transistor and the source of every GaN power transistor for clamping the positive turn-on gate voltage and the negative turn-off gate voltage.

13. The gate driver of claim 12 , wherein the clamp circuit comprises a diode clamp.

14. The gate driver of claim 10 , integrated with a driver controller.

15. A power semiconductor switching stage comprising:
a hybrid power semiconductor switching device comprising: a high-side switch and a low-side switch connected in series in a half-bridge configuration, wherein:
the high-side switch is a Gallium Nitride (GaN) semiconductor power switching device, implemented with a plurality of power transistors connected in parallel, wherein every power transistor of the high-side switch is an enhancement-mode GaN power transistor, having a drain, a source and a gate;
the low-side switch is a Silicon (Si) semiconductor power switching device, implemented with a plurality of power transistors connected in parallel, wherein every power transistor of the low-side switch is an enhancement-mode Si MOSFET, having a drain, a source and a gate;
the drain of every GaN power transistor is connected to a DC bus, the source of every GaN power transistor is connected to a switch node, the drain of every Si MOSFET is connected to the common switch node, and the source of every Si MOSFET is connected to a source bus;
a gate driver comprising a MOSFET half-bridge gate driver comprising a high-side driver and a low-side driver;
a gate drive output of the low-side driver being connected to the gate of every Si MOSFET through a first gate drive circuit comprising a gate resistor to provide a gate drive of a first voltage range for driving the plurality of Si MOSFETs;
a gate drive output of the high-side driver being connected to the gate of every GaN power transistor through a second gate drive circuit comprising a gate resistor and a voltage level shift circuit to provide a gate drive of a second voltage range, different from the first voltage range, for driving the plurality of GaN power transistors.

16. The power semiconductor switching stage of claim 15 wherein, for a power supply voltage V DD , said first voltage range for driving the plurality of Si MOSFETs is in a range from 0V to V DD , and t

Assignees

• Gan Systems Inc

Inventors

• Lu Juncheng
• Spaziani Larry

Classifications

• H03K17/6871 Primary

  the output circuit comprising more than one controlled field-effect transistor · CPC title

• H03K2217/0072

  Low side switches, i.e. the lower potential [DC] or neutral wire [AC] being directly connected to the switch and not via the load · CPC title

• Y02B70/10

  Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes · CPC title

• H03K2217/0063

  High side switches, i.e. the higher potential [DC] or life wire [AC] being directly connected to the switch and not via the load · CPC title

• H03K2217/0081

  Power supply means, e.g. to the switch driver · CPC title