Semiconductor devices

Patent metadata

Field	Value
Publication number	US-11670680-B2
Application number	US-202117559347-A
Country	US
Kind code	B2
Filing date	Dec 22, 2021
Priority date	May 17, 2019
Publication date	Jun 6, 2023
Grant date	Jun 6, 2023

Abstract

A semiconductor device including: an active pattern on a substrate, the active pattern including a recess, the recess having a “V” shape; a growth prevention pattern on the recess; gate structures on portions of the active pattern at opposite sides of the recess; channels spaced apart from each other in a vertical direction perpendicular to an upper surface of the substrate, each of the channels extending through one of the gate structures; and a source/drain layer on the growth prevention pattern, the source/drain layer contacting the channels.

First claim

What is claimed is:

1. A semiconductor device, comprising;
an active pattern on a substrate, the active pattern including a recess on its upper surface;
gate structures on a first portion of the active pattern at a first side of the recess and a second portion of the active pattern at a second side of the recess;
channels spaced apart from each other in a vertical direction perpendicular to an upper surface of the substrate, each of the channels extending through one of the gate structures; and
a source/drain layer on the active pattern, the source/drain layer being connected to the channels and including a semiconductor material doped with impurities,
wherein an impurity concentration of the source/drain layer between the channels at the same level varies from a first sidewall of a first channel of the channels to a second sidewall of a second channel of the channels facing the first sidewall of the first channel, the impurity concentration having a first impurity concentration, a second impurity concentration, and the first impurity concentration in this order from the first sidewall to the second sidewall.

2. The semiconductor device of claim 1 , wherein an impurity concentration of the source/drain layer varies from a bottom toward a top thereof in a region adjacent the first sidewall of the one channel or the second sidewall of the another channel, the impurity concentration having the first impurity concentration and the second impurity concentration alternately and repeatedly changing in the vertical direction.

3. The semiconductor device of claim 1 , wherein the source/drain layer includes silicon doped with n-type impurities or silicon carbide doped with n-type impurities.

4. The semiconductor device of claim 1 , further comprising a growth prevention pattern on the recess.

5. The semiconductor device of claim 4 , further comprising an air gap between the growth prevention pattern and the source/drain layer.

6. The semiconductor device of claim 1 , further comprising an inner spacer on a sidewall of each of the gate structures between the channels, and a sidewall of each of the gate structures between an upper surface of the active pattern and a lowermost one of the channels.

7. A semiconductor device, comprising:
a first transistor including:
a first active pattern on a first region of a substrate, the first active pattern including a first recess on its upper surface, and the substrate including the first region and a second region;
first gate structures on portions of the first active pattern at opposite sides of the first recess;
first channels spaced apart from each other in a vertical direction perpendicular to an upper surface of the substrate, each of the first channels extending through one of the first gate structures; and
a first source/drain layer on the first recess of the first active pattern, the first source/drain layer being connected to the first channels; and

a second transistor including:
a second active pattern on the second region of the substrate, the second active pattern including a second recess on its upper surface, the second recess having a “V” shape;
a growth prevention pattern on the second recess of the second active pattern;
second gate structures on portions of the second active pattern at opposite sides of the second recess;
second channels spaced apart from each other in the vertical direction, each of the second channels extending through one of the second gate structures; and
a second source/drain layer on the growth prevention pattern, the second source/drain layer being connected to the second channels.

8. The semiconductor device of claim 7 , wherein the first source/drain layer includes silicon-germanium doped with p-type impurities, and the second source/drain layer includes silicon doped with n-type impurities or silicon carbide doped with n-type impurities.

9. The semiconductor device of claim 8 , father comprising a leakage prevention pattern at an upper portion of the first active pattern adjacent to a bottom surface of the first source/drain layer, the leakage prevention pattern being doped with n-type impurities.

10. The semiconductor device of claim 8 , wherein the first recess has a concave shape.

11. The semiconductor device of claim 8 , wherein the second source/drain layer includes a first epitaxial layer on a sidewall of each of the second channels, and a second epitaxial layer adjacent to the first epitaxial layers, and
wherein an impurity concentration of the second epitaxial layer is higher than that of the first epitaxial layer.

12. The semiconductor device of claim 8 , further comprising a first air gap between the growth prevention pattern and the second source/drain layer.

13. The semiconductor device of claim 8 , further comprising an inner spacer on a sidewall of a first portion of the second gate structure between the second channels, and on a sidewall of a second portion of the second gate structure between an upper surface of the second active pattern and a lowermost one of the second channels.

14. The semiconductor device of claim 13 , wherein the inner spacer includes a material substantially the same as that of the growth prevention pattern.

15. The semiconductor device of claim 13 , further comprising a second air gap between the inner spacer and the second source/drain layer.

16. A semiconductor device, comprising:
first channels on a first region of a substrate, the first channels being spaced apart from each other in a vertical direction perpendicular to an upper surface of the substrate, the substrate including the first region and a second region;
a first gate structure on the first region of the substrate, the first gate structure disposed adjacent to at least a portion of a surface of each of the first channels;
a first source/drain layer on a portion of the substrate at each of opposite sides of the first gate structure, the first source/drain layer being connected to the first channels and including:
a first epitaxial layer extending in the vertical direction on sidewalls of the first channels; and
a second epitaxial layer on a surface of the first epitaxial layer, the second epitaxial layer having a second impurity concentration greater than the first impurity concentration;

second channels on the second region of the substrate, the second channels being spaced apart from each other in the vertical direction;
a second gate structure on the second region of the substrate, the second gate structure disposed adjacent to at least a portion of a surface of each of the second channels;
a second source/drain layer on a portion of the substrate at each of opposite sides of the second gate structure, the second source/drain layer being connected to the second channels and including;
a third epitaxial layer extending in the vertical direction on a sidewall of each of the second channels, the third epitaxial layer having a third impurity concentration; and
a fourth epitaxial layer on a surface of the third epitaxial layers, the fourth epitaxial layer having a fourth impurity concentration greater than the third impurity concentration.

17. The semiconductor device of claim 16 , wherein the first source/drain layer includes silicon-germanium doped with p-type impurities, and the second source/drain layer includes silicon doped with n-type impurities or silicon carbide doped with n-type impurities.

18. The semiconductor device of claim 16 , further comprising a fifth epitaxial layer on the first and second epitaxial layers, the fifth epitaxial layer h

Assignees

• Samsung Electronics Co Ltd

Inventors

• Jung Sujin
• Kim Kihwan
• Jang Sunguk
• Cho Youngdae

Classifications

• B82Y10/00

  Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic · CPC title

• H10D64/513

  within recesses in the substrate, e.g. trench gates, groove gates or buried gates · CPC title

• H10D64/258

  characterised by the relative positions of the source or drain electrodes with respect to the gate electrode · CPC title

• H10D62/8325

  Silicon carbide · CPC title

• H10D62/213

  Channel regions of field-effect devices · CPC title