Semiconductor devices and method of fabricating the same

Patent metadata

Field	Value
Publication number	US-11664453-B2
Application number	US-202117192301-A
Country	US
Kind code	B2
Filing date	Mar 4, 2021
Priority date	Jul 3, 2020
Publication date	May 30, 2023
Grant date	May 30, 2023

Abstract

A semiconductor device includes a substrate including a fin-type active region, the fin-type active region extending in a first direction; a plurality of channel layers on the fin-type active region, the plurality of channel layers including an uppermost channel layer, a lowermost channel layer, and an intermediate channel layer isolated from direct contact with each other in a direction perpendicular to an upper surface of the substrate; a gate electrode surrounding the plurality of channel layers and extending in a second direction intersecting the first direction; a gate insulating film between the plurality of channel layers and the gate electrode; and source/drain regions electrically connected to the plurality of channel layers. In a cross section taken in the second direction, the uppermost channel layer has a width greater than a width of the intermediate channel layer.

First claim

What is claimed is:

1. A semiconductor device comprising:
a substrate including a fin-type active region, the fin-type active region extending in a first direction parallel to an upper surface of the substrate;
a plurality of channel layers on the fin-type active region, the plurality of channel layers including an uppermost channel layer, a lowermost channel layer, and an intermediate channel layer isolated from direct contact with each other in a direction perpendicular to the upper surface of the substrate;
a gate electrode surrounding the plurality of channel layers and extending in a second direction, the second direction parallel to the upper surface of the substrate and intersecting the first direction;
a gate insulating film between the plurality of channel layers and the gate electrode; and
source/drain regions electrically connected to the plurality of channel layers,
wherein in a cross section taken in the second direction, the uppermost channel layer has a width greater than a width of the intermediate channel layer.

2. The semiconductor device of claim 1 , wherein, in the cross section taken in the second direction, the width of the intermediate channel layer is less than a width of the lowermost channel layer.

3. The semiconductor device of claim 1 , wherein, in the cross section taken in the second direction, the uppermost channel layer has downwardly inclined side surfaces.

4. The semiconductor device of claim 1 , wherein, in the cross section taken in the second direction, the lowermost channel layer has upwardly inclined side surfaces.

5. The semiconductor device of claim 1 , wherein, in the cross section taken in the second direction, both side surfaces of the intermediate channel layer have a convex shape.

6. The semiconductor device of claim 1 , wherein, in the cross section taken in the second direction, a difference in the width of the intermediate channel layer and the width of the uppermost channel layer is in a range of 1 nm to 10 nm.

7. The semiconductor device of claim 1 , wherein, in a cross section taken in the first direction, the intermediate channel layer has a width equal to the width of the uppermost channel layer.

8. The semiconductor device of claim 1 , wherein an upper surface of the uppermost channel layer includes a protruding edge portion and the protruding edge portion extends in the first direction.

9. The semiconductor device of claim 1 , wherein, in a cross section taken in the first direction, the uppermost channel layer has a flat upper surface.

10. The semiconductor device of claim 1 , further comprising:
gate spacers on both side surfaces of the gate electrode, respectively, in a cross section taken in the first direction.

11. The semiconductor device of claim 1 , further comprising:
a plurality of internal spacers in between portions of the gate electrode between the plurality of channel layers and the source/drain regions.

12. The semiconductor device of claim 1 , further comprising:
contact plugs connected to the source/drain regions and extending in the direction perpendicular to the upper surface of the substrate.

13. The semiconductor device of claim 1 , wherein the source/drain regions and the plurality of channel layers include the same crystal orientation.

14. The semiconductor device of claim 1 , wherein the lowermost channel layer is over an upper region of the fin-type active region.

15. A semiconductor device comprising:
a substrate including a fin-type active region extending in a first direction, the first direction parallel to an upper surface of the substrate;
a plurality of channel layers on the fin-type active region, the plurality of channel layers isolated from direct contact with each other in a direction perpendicular to the upper surface of the substrate and including an uppermost channel layer, a lowermost channel layer, and an intermediate channel layer;
a gate electrode surrounding the plurality of channel layers and extending in a second direction, the second direction parallel to the upper surface of the substrate and intersecting the first direction;
a gate insulating film between the plurality of channel layers and the gate electrode; and
source/drain regions electrically connected to the plurality of channel layers,
wherein in a cross section taken in the second direction, the lowermost channel layer has a width greater than a width of the intermediate channel layer and has an upwardly inclined side surface.

16. The semiconductor device of claim 15 , wherein, in the cross section taken in the second direction, an upper surface of the uppermost channel layer has a protruding edge portion.

17. The semiconductor device of claim 16 , wherein the protruding edge portion extends in the first direction.

18. The semiconductor device of claim 15 , wherein, in the cross section taken in the second direction, the uppermost channel layer has a width greater than the width of the intermediate channel layer.

19. The semiconductor device of claim 18 , wherein, in the cross section taken in the second direction, the uppermost channel layer has a downwardly inclined side surface.

20. A semiconductor device comprising;
a substrate including a fin-type active region extending in a first direction, the first direction parallel to an upper surface of the substrate;
a plurality of channel layers on the fin-type active region, the plurality of channel layers isolated from direct contact with each other in a direction perpendicular to the upper surface of the substrate and including an uppermost channel layer, a lowermost channel layer, and an intermediate channel layer;
a gate electrode surrounding the plurality of channel layers and extending in a second direction, the second direction parallel to the upper surface of the substrate and intersecting the first direction;
a gate insulating film between the plurality of channel layers and the gate electrode; and
source/drain regions electrically connected to the plurality of channel layers,
wherein, in a cross section taken in the second direction, the uppermost channel layer and the lowermost channel layer each have a width greater than the width of the intermediate channel layer, and an upper surface of the uppermost channel layer has a protruding edge portion.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Jaemun
• Kim Dahye
• Kim Jinbum
• Kim Gyeom
• Kim Dohee
• Kim Dongwoo
• Lee Seunghun

Classifications

• H10D30/6735

  having gates fully surrounding the channels, e.g. gate-all-around · CPC title

• H10D62/121

  oriented parallel to substrates · CPC title

• H10D30/6757 Primary

  characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715) · CPC title

• H10D62/405

  Orientations of crystalline planes · CPC title

• H10D84/0158

  the components including FinFETs · CPC title