System and method to enhance noise performance in a delta sigma converter

Patent metadata

Field	Value
Publication number	US-11658678-B2
Application number	US-202117395983-A
Country	US
Kind code	B2
Filing date	Aug 6, 2021
Priority date	Aug 10, 2020
Publication date	May 23, 2023
Grant date	May 23, 2023

Abstract

Systems and methods for improving noise efficiency in a Delta Sigma modulator. A bypass scheme for a noise splitter is disclosed that reduces toggling activity for small signals. In particular, a sample-by-sample bypass noise splitter is disclosed that includes a noise splitting module and a bypass line. The bypass line bypasses the noise splitting module when signals are below a selected threshold, increasing efficiency of the system.

First claim

What is claimed is:

1. A sample-by-sample bypass noise splitter, comprising:
a noise splitting module configured to split an input signal into a plurality of split signals, wherein each of the plurality of split signals is smaller than the input signal, wherein the noise splitting module includes a first multiplexor to process a first output; and
a bypass line configured to pass the input signal directly through to an output line, wherein the bypass line includes a second multiplexor to process a second output and least significant bits of the input signal;
wherein signals above a selected threshold are directed to the noise splitting module and wherein signals below the selected threshold are directed to the bypass line.

2. The bypass noise splitter of claim 1 , wherein the bypass line is configured to pass a set of least significant bits of the input signal through to the output line.

3. The bypass noise splitter of claim 1 , wherein the plurality of split signals includes a first signal including least significant bits of the input signal and a second signal including most significant bits of the input signal.

4. The bypass noise splitter of claim 1 , wherein the noise splitting module comprises a sigma delta loop configured to split the input signal.

5. The bypass noise splitter of claim 4 , wherein:
the sigma delta loop is a one of a first order sigma delta loop and a higher-order sigma delta loop;
the sigma delta loop is configured to split the input signal into a plurality of component outputs; and
a sum of the plurality of component outputs equals the input signal.

6. The bypass noise splitter of claim 1 , wherein the noise splitting module includes an adder configured to add a second signal to the input signal.

7. The bypass noise splitter of claim 6 , wherein the adder is a first adder and wherein the noise splitting module includes a second adder and a quantizer configured to truncate a second adder output to provide a first output.

8. The bypass noise splitter of claim 7 , wherein the noise splitting module includes a register configured to filter a quantizer output and further configured to feed back a filtered quantizer output and add the filtered quantizer output to a first adder output.

9. The bypass noise splitter of claim 8 , wherein the register is configured to utilize a second adder on a subsequent cycle to add the filtered quantizer output to the first adder output.

10. The bypass noise splitter of claim 1 , wherein the bypass line further comprises a third adder configured to process the input signal and a first output to generate a second output.

11. The bypass noise splitter of claim 1 , wherein when signals are below the selected threshold, the noise splitting module is disabled and the first multiplexor is configured to output a zero, and the second multiplexor is configured to output the least significant bits of the input signal.

12. The bypass noise splitter of claim 1 , wherein when signals are below the selected threshold, the noise splitting module is disabled.

13. The bypass noise splitter of claim 12 , further comprising a hold-off module, wherein signals below the selected threshold are directed to the hold-off module, and wherein the hold-off module is configured to postpone disabling the noise splitting module for a selected time period.

14. The bypass module of claim 1 , wherein a first split signal of the plurality of split signals includes a first number of least significant bits, wherein the bypass line is configured to pass through a second number of least significant bits of the input signal, and wherein the first number of least significant bits is different from the second number of least significant bits.

15. A converter having enhanced noise performance, comprising:
an interpolator configured to receive an input signal;
a noise splitter including a noise splitting module and a bypass line, configured to receive an interpolated signal and output a plurality of parallel output signals;
a plurality of rotational scramblers coupled to the noise splitter configured to apply discrete element modeling to each of the plurality of parallel output signals and output a respective plurality of DEM output signals; and
a plurality of digital-to-analog converters (DACs) coupled to the rotational scramblers configured to convert each of the plurality of DEM output signals to a respective analog signal;
wherein the noise splitter is a sample-to-sample bypass splitter, and wherein signals above a selected threshold are directed to the noise splitting module and wherein signals below the selected threshold are directed to the bypass line.

16. The converter of claim 15 , wherein when signals are below the selected threshold, the noise splitter is configured to disable the noise splitting module.

17. The converter of claim 16 , wherein the noise splitter includes a hold-off module, wherein signals below the selected threshold are directed to the hold-off module, and wherein the hold-off module is configured to postpone disabling the noise splitting module for a selected time period.

18. A method for a sample-by-sample bypass noise splitter, comprising:
receiving an input signal;
determining whether the input signal is above a selected threshold;
when the input signal is above the selected threshold:
splitting the input signal into a plurality of split signals, wherein each of the plurality of split signals is smaller than the input signal, and
processing a first output at a first multiplexor; and

when the input signal is below the selected threshold:
passing the input signal directly through to an output line, and
processing a second output and least significant bits of the input signal at a second multiplexor.

19. The method of claim 18 , wherein passing the input signal directly through to the output line comprises passing a set of least significant bits of the input signal through to the output line.

20. The method of claim 18 , wherein when the input signal is below the selected threshold, outputting a zero from the first multiplexor, and outputting the least significant bits of the input signal at the second multiplexor.

Assignees

• Analog Devices Inc

Inventors

• Bandyopadhyay Abhishek
• Birdsong Preston S
• Spirer Adam R

Classifications

• H03M3/502

  Details of the final digital/analogue conversion following the digital delta-sigma modulation · CPC title

• H03M7/3042

  the modulator being of the error feedback type, i.e. having loop filter stages in the feedback path only · CPC title

• H03M3/368 Primary

  of noise other than the quantisation noise already being shaped inherently by delta-sigma modulators · CPC title

• H03M3/412

  characterised by the number of quantisers and their type and resolution · CPC title

• H03M7/3017

  Arrangements specific to bandpass modulators · CPC title