Envelope dependent output stage scalability

Patent metadata

Field	Value
Publication number	US-9768800-B1
Application number	US-201615264421-A
Country	US
Kind code	B1
Filing date	Sep 13, 2016
Priority date	Sep 13, 2016
Publication date	Sep 19, 2017
Grant date	Sep 19, 2017

Abstract

An apparatus comprises a digital to analog converter (DAC) circuit configured to receive a time-varying a digital input signal and convert the digital input signal to an analog output signal, an output amplifier circuit operatively coupled to the output of the DAC circuit, a peak detector circuit operatively coupled to the input the DAC and configured to produce a signal envelope of the digital input signal, and logic circuitry. The logic circuitry is operatively coupled to the peak detector circuit and is configured to detect when the signal envelope satisfies a specified threshold value; and to adjust a drive capability of an output amplifier circuit of the DAC circuit according to the signal envelope.

First claim

What is claimed is:

1. An apparatus comprising:
a digital-to-analog converter (DAC) circuit configured to receive a tune-varying a digital input signal and convert the digital input signal to an analog output signal;
an amplifier circuit operatively coupled to an output of the DAC circuit;
a peak detector circuit operatively coupled to an input the DAC circuit and configured to produce a signal envelope of the digital input signal; and
logic circuitry operatively coupled to the peak detector circuit and configured to detect when the signal envelope satisfies a specified threshold value; and
adjust a drive capability of the amplifier circuit according to the signal envelope.

2. The apparatus of claim 1 , wherein the logic circuitry is configured to cycle the DAC circuit through a blanking state and a conversion state, and to adjust the drive capability of the amplifier circuit during the blanking state of the DAC circuit.

3. The apparatus of claim 1 , wherein the logic circuitry is configured to adjust a bias current of the amplifier circuit.

4. The apparatus of claim 1 , wherein the logic circuitry is configured to adjust a bias current in an output stage of the amplifier circuit.

5. The apparatus of claim 1 , wherein the logic circuitry is configured to:
detect when the signal envelope is greater than a first specified threshold value;
increase the drive capability of the amplifier circuit from a first drive level to a second drive level when the signal envelope is greater than the first specified threshold value;
detect when the signal envelope is less than a second specified threshold value, wherein the second specified threshold value is less than the first specified threshold value; and
decrease the drive capability of the amplifier circuit from the second drive level to the first drive level when the signal envelope is less than the second specified threshold value.

6. The apparatus of claim 5 , wherein the logic circuitry is configured to:
detect when the signal envelope is greater than a third specified threshold value; wherein the third specified threshold value is greater than the first specified threshold value;
increase the drive capability of the amplifier circuit from the drive level to a third drive level when the signal envelope is greater than the third specified threshold value;
detect when the signal envelope is less than a fourth specified threshold value, wherein the fourth specified threshold value is less than the third specified threshold value and greater than the first specified threshold value; and
decrease the drive capability of the amplifier circuit from the third drive level to the second drive level when the signal envelope is less than the fourth specified threshold value.

7. The apparatus of claim 1 , wherein the amplifier circuit includes a differential output stage and the logic circuitry is configured to adjust the drive capability of the differential output stage according to the signal envelope.

8. The apparatus of claim 1 , wherein the DAC is a current steering DAC circuit and the amplifier circuit is a current to voltage amplifier circuit.

9. The apparatus of claim 1 , wherein the amplifier circuit includes a plurality of current mirror circuits and the logic circuitry is configured to scale the drive capability of the amplifier circuit by enabling and disabling the plurality of current mirror circuits according to the signal envelope.

10. The apparatus of claim 1 , wherein the peak detector circuit is configured to produce a decaying signal envelope when the digital input signal decreases; and
wherein the logic circuitry is configured to decrease the drive capability of the amplifier circuit when the decaying signal envelope decreases below a specified threshold value.

11. The apparatus of claim 10 , wherein the logic circuitry is configured to decrease the drive capability of the amplifier circuit when the decaying signal envelope decreases below a specified fraction of the signal envelope resulting from a full scale digital input signal.

12. A method of controlling operation of a sigma delta digital-to-analog converter (DAC) circuit, the method comprising:
receiving a time-varying a digital input signal at the sigma delta DAC circuit;
producing a signal envelope of the digital input signal;
detecting that the signal envelope satisfies a specified threshold value; and
adjusting a drive capability of an amplifier circuit of the sigma delta DAC circuit according to the signal envelope.

13. The method of claim 12 , including cycling the sigma delta DAC circuit through a blanking state and a conversion state, wherein the adjusting the drive capability includes adjusting the drive capability during the blanking state of the sigma delta DAC circuit.

14. The method of claim 12 , wherein the adjusting the drive capability includes:
detecting when the signal envelope is greater than a first specified threshold value;
increasing the drive capability of the output amplifier from a first drive level to a second drive level when the signal envelope is greater than the first specified threshold value;
detecting when the signal envelope is less than a second specified threshold value, wherein the second specified threshold value is less than the first specified threshold value; and
decreasing the drive capability of the output amplifier from the second drive level to the first drive level when the signal envelope is less than the second specified threshold value.

15. The method of claim 14 , wherein the adjusting the drive capability includes:
detecting when the signal envelope is greater than a third specified threshold value, wherein the third specified threshold value is greater than the first specified threshold value;
increasing the drive capability of the amplifier circuit from the drive level to a third drive level when the signal envelope is greater than the third specified threshold value;
detecting when the signal envelope is less than a fourth specified threshold value; wherein the fourth specified threshold value is less than the third specified threshold value and greater than the first specified threshold value; and
decreasing the drive capability of the amplifier circuit from the third drive level to the second drive level when the signal envelope is less than the fourth specified threshold value.

16. The method of claim 12 ; wherein adjusting the drive capability of the amplifier circuit includes scaling a bias current of the output stage of the output amplifier according to the detected signal envelope.

17. A sigma delta digital-to-analog converter circuit comprising:
an interpolation filter circuit configured to receive a time-varying digital input signal;
a modulator circuit operatively coupled to the interpolation filter circuit and configured to produce a modulated digital signal having a different number of bits than the time-varying digital input signal;
a digital to analog converter (DAC) circuit operatively coupled to the modulator circuit and configured to convert the modulated digital signal to an analog output signal;
an output amplifier circuit operatively coupled to an output of the DAC circuit;
a peak detector circuit operatively coupled to the interpolation filter circuit and configured to produce a signal envelope of the time-varying digital input signal; and
logic circuitry operatively coupled to the peak detector circuit and configured to detect when the signal envelope satisfies a specified threshold value and to adjust a drive capability of the output amplifier according to

Assignees

• Analog Devices Inc

Inventors

• Nguyen Khiem Quang

Classifications

• H03F2203/45154

  the bias at the input of the amplifying transistors being controlled · CPC title

• H03M3/50 Primary

  Digital/analogue converters using delta-sigma modulation as an intermediate step (digital delta-sigma modulators per se H03M7/3004) · CPC title

• H03F2200/435

  A peak detection being used in a signal measuring circuit in a controlling circuit of an amplifier · CPC title

• H03F2200/102

  A non-specified detector of a signal envelope being used in an amplifying circuit · CPC title

• H03M3/322

  Continuously compensating for, or preventing, undesired influence of physical parameters (periodically, e.g. by using stored correction values, H03M3/378) · CPC title